专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08026507B2 Two terminal quantum device using MOS capacitor structure 有权
标题翻译：两端子量子器件采用MOS电容器结构
公开(公告)号：US08026507B2
公开(公告)日：2011-09-27
申请号：US12544805
申请日：2009-08-20
申请人： Tathagata Chatterjee , Henry Litzmann Edwards , Chris Bowen
发明人： Tathagata Chatterjee , Henry Litzmann Edwards , Chris Bowen
IPC分类号： H01L29/06 , H01L21/335
CPC分类号： H01L29/94
摘要： A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
摘要翻译：公开了一种形成为MOS电容的门控量子阱器件。量子阱是在MOS栅极下面的小于20纳米宽的反转区域。该器件可以以任一极性制造，并且被集成到配置为量子点器件或量子线器件的CMOS IC中。该装置可以作为精密电荷泵进行操作，加入少量载流子注入区以加速填充。

2. 发明申请

US20100045365A1 TWO TERMINAL QUANTUM DEVICE USING MOS CAPACITOR STRUCTURE 有权
标题翻译：使用MOS电容结构的两个终端量子器件
公开(公告)号：US20100045365A1
公开(公告)日：2010-02-25
申请号：US12544805
申请日：2009-08-20
申请人： Tathagata CHATTERJEE , Henry Litzmann EDWARDS , Chris BOWEN
发明人： Tathagata CHATTERJEE , Henry Litzmann EDWARDS , Chris BOWEN
IPC分类号： G05F1/10 , H01L29/66 , H01L21/336
CPC分类号： H01L29/94
摘要： A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
摘要翻译：公开了一种形成为MOS电容的门控量子阱器件。量子阱是在MOS栅极下面的小于20纳米宽的反转区域。该器件可以以任一极性制造，并且被集成到配置为量子点器件或量子线器件的CMOS IC中。该装置可以作为精密电荷泵进行操作，加入少量载流子注入区以加速填充。

3. 发明申请

US20090057651A1 Gated Quantum Resonant Tunneling Diode Using CMOS Transistor with Modified Pocket and LDD Implants 有权
标题翻译：使用具有修改的口袋和LDD植入物的CMOS晶体管的门控量子谐振隧道二极管
公开(公告)号：US20090057651A1
公开(公告)日：2009-03-05
申请号：US12204604
申请日：2008-09-04
申请人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
发明人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
IPC分类号： H01L29/12 , H01L21/329
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L27/0922 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
摘要翻译：公开了一种选通谐振隧道二极管（GRTD），其在栅极电介质层上方具有金属氧化物半导体（MOS）栅极，该栅极电介质层被偏置以在两个势垒区域之间形成反转层，导致量子阱小于15纳米宽。与阻挡区域相邻的源极和漏极区域控制流入和流出量子阱的电流。 GRTD可以集成在CMOS IC中作为量子点或量子线器件。 GRTD可以在负电导模式，电荷泵模式和辐射发射模式下操作。

4. 发明授权

US07683364B2 Gated quantum resonant tunneling diode using CMOS transistor with modified pocket and LDD implants 有权
标题翻译：门控量子谐振隧道二极管采用CMOS晶体管，具有改进的口袋和LDD种植体
公开(公告)号：US07683364B2
公开(公告)日：2010-03-23
申请号：US12204604
申请日：2008-09-04
申请人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
发明人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
IPC分类号： H01L29/88 , H01L29/775 , H01L21/336
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L27/0922 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
摘要翻译：公开了一种选通谐振隧道二极管（GRTD），其在栅极电介质层上方具有金属氧化物半导体（MOS）栅极，该栅极电介质层被偏置以在两个势垒区域之间形成反转层，导致量子阱小于15纳米宽。与阻挡区域相邻的源极和漏极区域控制流入和流出量子阱的电流。 GRTD可以集成在CMOS IC中作为量子点或量子线器件。 GRTD可以在负电导模式，电荷泵模式和辐射发射模式下操作。

5. 发明申请

US20090152626A1 Super Halo Formation Using a Reverse Flow for Halo Implants 审中-公开
标题翻译：超光晕使用反向流动为光晕植入物
公开(公告)号：US20090152626A1
公开(公告)日：2009-06-18
申请号：US11959032
申请日：2007-12-18
申请人： Ramesh Venugopal , Srinivasan Chakravarthi , Chris Bowen
发明人： Ramesh Venugopal , Srinivasan Chakravarthi , Chris Bowen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.
摘要翻译：集成电路中MOS晶体管的收缩尺寸需要从光晕离子注入工艺在口袋区域中更严格地分配掺杂剂。在常规制造工艺序列中，卤素掺杂剂分布在源极/漏极退火期间扩散。本发明是在源极/漏极退火之后执行卤素离子的集成电路中制造MOS晶体管的方法。在本发明的方法中，在卤素离子注入工艺之前，MOS栅极侧壁上的源极/漏极间隔物被去除。偏移金属硅化物的间隔物在晕轮植入物之后形成，并且可以是低k电介质材料以减小栅极至漏极电容。在源极/漏极间隔物被去除之后，压电应力层可以沉积在MOS栅极上，以提高MOS栅极的应力传递效率。还公开了体现本发明方法的集成电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式