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1. 发明授权

US07683364B2 Gated quantum resonant tunneling diode using CMOS transistor with modified pocket and LDD implants 有权
标题翻译：门控量子谐振隧道二极管采用CMOS晶体管，具有改进的口袋和LDD种植体
公开(公告)号：US07683364B2
公开(公告)日：2010-03-23
申请号：US12204604
申请日：2008-09-04
申请人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
发明人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
IPC分类号： H01L29/88 , H01L29/775 , H01L21/336
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L27/0922 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
摘要翻译：公开了一种选通谐振隧道二极管（GRTD），其在栅极电介质层上方具有金属氧化物半导体（MOS）栅极，该栅极电介质层被偏置以在两个势垒区域之间形成反转层，导致量子阱小于15纳米宽。与阻挡区域相邻的源极和漏极区域控制流入和流出量子阱的电流。 GRTD可以集成在CMOS IC中作为量子点或量子线器件。 GRTD可以在负电导模式，电荷泵模式和辐射发射模式下操作。

2. 发明授权

US08026507B2 Two terminal quantum device using MOS capacitor structure 有权
标题翻译：两端子量子器件采用MOS电容器结构
公开(公告)号：US08026507B2
公开(公告)日：2011-09-27
申请号：US12544805
申请日：2009-08-20
申请人： Tathagata Chatterjee , Henry Litzmann Edwards , Chris Bowen
发明人： Tathagata Chatterjee , Henry Litzmann Edwards , Chris Bowen
IPC分类号： H01L29/06 , H01L21/335
CPC分类号： H01L29/94
摘要： A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
摘要翻译：公开了一种形成为MOS电容的门控量子阱器件。量子阱是在MOS栅极下面的小于20纳米宽的反转区域。该器件可以以任一极性制造，并且被集成到配置为量子点器件或量子线器件的CMOS IC中。该装置可以作为精密电荷泵进行操作，加入少量载流子注入区以加速填充。

3. 发明申请

US20090057651A1 Gated Quantum Resonant Tunneling Diode Using CMOS Transistor with Modified Pocket and LDD Implants 有权
标题翻译：使用具有修改的口袋和LDD植入物的CMOS晶体管的门控量子谐振隧道二极管
公开(公告)号：US20090057651A1
公开(公告)日：2009-03-05
申请号：US12204604
申请日：2008-09-04
申请人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
发明人： Henry Litzmann Edwards , Chris Bowen , Tathagata Chatterjee
IPC分类号： H01L29/12 , H01L21/329
CPC分类号： H01L29/882 , H01L27/0629 , H01L27/0811 , H01L27/0922 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
摘要翻译：公开了一种选通谐振隧道二极管（GRTD），其在栅极电介质层上方具有金属氧化物半导体（MOS）栅极，该栅极电介质层被偏置以在两个势垒区域之间形成反转层，导致量子阱小于15纳米宽。与阻挡区域相邻的源极和漏极区域控制流入和流出量子阱的电流。 GRTD可以集成在CMOS IC中作为量子点或量子线器件。 GRTD可以在负电导模式，电荷泵模式和辐射发射模式下操作。

4. 发明授权

US07692217B2 Matched analog CMOS transistors with extension wells 有权
标题翻译：具有扩展阱的匹配模拟CMOS晶体管
公开(公告)号：US07692217B2
公开(公告)日：2010-04-06
申请号：US11948172
申请日：2007-11-30
申请人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
发明人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
IPC分类号： H01L27/148
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及集成电路。集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。还公开了其他装置，方法和系统。

5. 发明申请

US20090079446A1 Method to Accurately Estimate the Source and Drain Resistance of a MOSFET 有权
标题翻译：准确估计MOSFET的源极和漏极电阻的方法
公开(公告)号：US20090079446A1
公开(公告)日：2009-03-26
申请号：US11860993
申请日：2007-09-25
申请人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
发明人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.
摘要翻译： MOS晶体管的参数（也称为MOSFET）的参数（如阈值电位）的测量需要源极和漏极串联电阻的精确估计。在与MOSFET的连接包括显着的外部串联电阻的情况下，如在部分制造或去处理的探测晶体管中发生的那样，也需要外部电阻的精确估计。本发明包括一种用于估计MOSFET的串联电阻的方法，包括与MOSFET连接的电阻（例如探针触点）。该方法适用于可在源极，漏极，栅极和衬底端子上访问的任何MOSFET，并且不需要其他测试结构或特殊连接，例如开尔文连接。

6. 发明申请

US20090159967A1 SEMICONDUCTOR DEVICE HAVING VARIOUS WIDTHS UNDER GATE 有权
标题翻译：半导体器件在门下有不同的宽度
公开(公告)号：US20090159967A1
公开(公告)日：2009-06-25
申请号：US11959921
申请日：2007-12-19
申请人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Gabriel J. Gomez
发明人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Gabriel J. Gomez
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/1045 , H01L29/4238 , H01L29/6659 , H01L29/7833
摘要： One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及形成在半导体本体上的半导体器件。在该器件中，源极和漏极区域围绕栅电极的侧边缘形成在主体中并且彼此分开栅极长度。被配置为允许带电载流子在器件操作期间选择性地在源极和漏极区域之间流动的沟道区域在栅极电极下方具有不同的宽度。这些宽度通常垂直于栅极长度。还公开了其他装置，方法和系统。

7. 发明申请

US20090140346A1 MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS 有权
标题翻译：具有扩展孔的匹配模拟CMOS晶体管
公开(公告)号：US20090140346A1
公开(公告)日：2009-06-04
申请号：US11948172
申请日：2007-11-30
申请人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
发明人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及集成电路。集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。还公开了其他装置，方法和系统。

8. 发明授权

US09484435B2 MOS transistor with varying channel width 有权
标题翻译：具有不同通道宽度的MOS晶体管
公开(公告)号：US09484435B2
公开(公告)日：2016-11-01
申请号：US11959921
申请日：2007-12-19
申请人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Gabriel J. Gomez
发明人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Gabriel J. Gomez
IPC分类号： H01L23/58 , H01L29/66 , H01L21/28 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28114 , H01L29/1045 , H01L29/4238 , H01L29/6659 , H01L29/7833
摘要： One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及形成在半导体本体上的半导体器件。在该器件中，源极和漏极区域围绕栅电极的侧边缘形成在主体中并且彼此分开栅极长度。被配置为允许带电载流子在器件操作期间选择性地在源极和漏极区域之间流动的沟道区域在栅极电极下方具有不同的宽度。这些宽度通常垂直于栅极长度。还公开了其他装置，方法和系统。

9. 发明授权

US07687856B2 Body bias to facilitate transistor matching 有权
标题翻译：器件偏置，便于晶体管匹配
公开(公告)号：US07687856B2
公开(公告)日：2010-03-30
申请号：US11746887
申请日：2007-05-10
申请人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Xiaoju Wu
发明人： Henry Litzmann Edwards , Tathagata Chatterjee , Mohamed Kamel Mahmoud , Xiaoju Wu
IPC分类号： H01L29/02 , H01L29/04
CPC分类号： H01L29/1087 , H01L29/1045 , H01L29/1083 , H01L29/78 , H03F1/301 , H03F3/45183 , H03F2203/45342
摘要： One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.
摘要翻译：本发明的一个实施例涉及一种用于晶体管匹配的方法。在该方法中，通过向第一晶体管施加具有第一极性的栅极 - 源极偏置，在第一晶体管内形成沟道。通过将具有第一极性的体源偏压施加到第一晶体管来减小第一晶体管的口腔注入区域中的势垒的幅度。通过向第一晶体管施加具有第一极性的漏极 - 源极偏置，使通过沟道的电流流动。还公开了其它方法和电路。

10. 发明授权

US07595649B2 Method to accurately estimate the source and drain resistance of a MOSFET 有权
标题翻译：准确估计MOSFET的源极和漏极电阻的方法
公开(公告)号：US07595649B2
公开(公告)日：2009-09-29
申请号：US11860993
申请日：2007-09-25
申请人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
发明人： Tathagata Chatterjee , Joe R. Trogolo , Kaiyuan Chen , Henry Litzmann Edwards
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.
摘要翻译： MOS晶体管的参数（也称为MOSFET）的参数（如阈值电位）的测量需要源极和漏极串联电阻的精确估计。在与MOSFET的连接包括显着的外部串联电阻的情况下，如在部分制造或去处理的探测晶体管中发生的那样，也需要外部电阻的精确估计。本发明包括一种用于估计MOSFET的串联电阻的方法，包括与MOSFET连接的电阻（例如探针触点）。该方法适用于可在源极，漏极，栅极和衬底端子上访问的任何MOSFET，并且不需要其他测试结构或特殊连接，例如开尔文连接。

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