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1. 发明申请

US20100033207A1 Fault Tolerant Integrated Circuit Architecture 有权
标题翻译：容错集成电路架构
公开(公告)号：US20100033207A1
公开(公告)日：2010-02-11
申请号：US12463040
申请日：2009-05-08
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A, Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A, Furciniti , Christopher E. Phillips
IPC分类号： H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

2. 发明申请

US20090134907A1 Fault Tolerant Integrated Circuit Architecture 失效
标题翻译：容错集成电路架构
公开(公告)号：US20090134907A1
公开(公告)日：2009-05-28
申请号：US12193015
申请日：2008-08-17
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

3. 发明授权

US5966534A Method for compiling high level programming languages into an integrated processor with reconfigurable logic 失效
标题翻译：将高级编程语言编译成具有可重构逻辑的集成处理器的方法
公开(公告)号：US5966534A
公开(公告)日：1999-10-12
申请号：US884377
申请日：1997-06-27
申请人： Laurence H. Cooke , Christopher E. Phillips , Dale Wong
发明人： Laurence H. Cooke , Christopher E. Phillips , Dale Wong
IPC分类号： G06F9/45 , G06F9/48 , G06F17/50 , G06F9/44
CPC分类号： G06F17/5045 , G06F8/4441 , G06F8/447 , G06F8/451
摘要： A method is presented for automatically compiling a high level computer program down into an application specific integrated circuit coupled with a generic microprocessor. The original source code is written in a standard programming language such as ANSI C. Source code analysis is performed by our compiler to automatically determine which blocks of logic are most appropriate for the application specific integrated circuit and which for the generic microprocessor. The complete layout of the application specific integrated circuit is automatically generated by our compiler. Object code for the microprocessor, with custom instructions to invoke the application specific integrated circuit, is also automatically generated by our compiler.
摘要翻译：提出了一种用于将高级计算机程序自动编译成与通用微处理器耦合的专用集成电路的方法。原始源代码以标准编程语言（如ANSI C）编写。源代码分析由我们的编译器执行，以自动确定哪个逻辑块最适合于专用集成电路以及通用微处理器。专用集成电路的完整布局由我们的编译器自动生成。微处理器的对象代码，具有调用专用集成电路的自定义指令，也由我们的编译器自动生成。

4. 发明授权

US5815736A Area and time efficient extraction circuit 失效
标题翻译：区域和时间有效的提取电路
公开(公告)号：US5815736A
公开(公告)日：1998-09-29
申请号：US451434
申请日：1995-05-26
申请人： Christopher E. Phillips , Narendra Sankar
发明人： Christopher E. Phillips , Narendra Sankar
IPC分类号： G06F7/76 , G06F7/00
CPC分类号： G06F7/76
摘要： The present invention is a data word extraction circuit that receives n data words DW.sub.x (for x equal 0 through n-1), where each of the data words DW.sub.x having m bit positions BP.sub.y (for y=0 through m-1). The circuit provides at least one of the data words DW.sub.x to an extraction circuit output responsive to an extraction indicator signal. Specifically, a group of data selector elements DSE.sub.y, each corresponding to a separate one of the bit positions BP.sub.y in the received data words. Each data selector element includes a data output DO.sub.y and a plurality of data inputs DI.sub.x. Each data input DI.sub.x is connected to receive a bit from the bit position BP.sub.y to which the data selector element DSE.sub.y corresponds, of a data word DW.sub.x to which the data input DI.sub.x corresponds. A select input is responsive to the extraction indicator signal such that the data selector element DSE.sub.y provides, at the data output, the bit received at one of the data inputs DI.sub.x that corresponds to the extraction indicator signal. The bits provided at the data outputs of the group of data selector elements are collectively provided to the extraction circuit output.
摘要翻译：本发明是一种数据字提取电路，其接收n个数据字DWx（x等于0到n-1），其中每个数据字DWx具有m位位置BPy（对于y = 0至m-1）。该电路根据提取指示符信号将数据字DWx中的至少一个提供给提取电路输出。具体地，一组数据选择器元素DSEy，每个对应于所接收的数据字中的位位置BPy中的一个位置。每个数据选择器元件包括数据输出DOy和多个数据输入DIx。每个数据输入DIx被连接以从数据输入DIx对应的数据字DWx接收与数据选择器元件DSEy对应的位位置BPy的位。选择输入响应于提取指示符信号，使得数据选择器元件DSEy在数据输出处提供在与提取指示符信号相对应的数据输入DIx之一处接收到的位。提供在数据选择器元件组的数据输出端的位被集中提供给提取电路输出。

5. 发明授权

US5546353A Partitioned decode circuit for low power operation 失效
标题翻译：用于低功耗操作的分区解码电路
公开(公告)号：US5546353A
公开(公告)日：1996-08-13
申请号：US450153
申请日：1995-05-26
申请人： Christopher E. Phillips , Narendra Sankar
发明人： Christopher E. Phillips , Narendra Sankar
IPC分类号： G06F9/30 , G11C8/00
CPC分类号： G06F9/30145
摘要： A partitioned decoder circuit responds to an address signal supplied at a decoder circuit input by providing a result data signal that corresponds to the address signal. Selection signal decoder circuitry asserts one or more of a plurality of decoder enable signals based upon the value of a decoder selection signal. A plurality of decoder circuit elements are each connected to receive a separate one of the asserted decoder enable signals. Each decoder circuit element includes a first clock input coupled to receive a precharge clock signal, an address input coupled to receive the address signal, address latching circuitry that latches the address signal in response to a polarity transition of the precharge clock signal, and a second clock input. Significantly, gated discharge clock signal generation circuitry of each decoder circuit element generates a gated discharge clock signal in response to the asserted decoder enable signal. The gated discharge clock signal is provided to the second clock input. A data output responds to the gated discharge clock signal being provided to the second clock input by providing an evaluation signal that corresponds to the latched address signal such that the result data signal includes the evaluation signal.
摘要翻译：分割解码器电路通过提供对应于地址信号的结果数据信号来响应在解码器电路输入处提供的地址信号。选择信号解码器电路基于解码器选择信号的值来确定多个解码器使能信号中的一个或多个。多个解码器电路元件各自被连接以接收所断言的解码器使能信号中的单独一个。每个解码器电路元件包括耦合以接收预充电时钟信号的第一时钟输入，耦合以接收地址信号的地址输入，响应于预充电时钟信号的极性转换而锁存地址信号的地址锁存电路，以及第二时钟输入时钟输入。重要的是，每个解码器电路元件的门控放电时钟信号产生电路响应于所确定的解码器使能信号产生门控放电时钟信号。门控放电时钟信号被提供给第二时钟输入。数据输出通过提供对应于锁存的地址信号的评估信号来响应提供给第二时钟输入的门控放电时钟信号，使得结果数据信号包括评估信号。

6. 发明授权

US5221865A Programmable input/output buffer circuit with test capability 失效
标题翻译：具有测试能力的可编程输入/输出缓冲电路
公开(公告)号：US5221865A
公开(公告)日：1993-06-22
申请号：US718677
申请日：1991-06-21
申请人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
发明人： Christopher E. Phillips , Michael G. Ahrens , Joseph G. Nolan, III , Laurence H. Cooke
IPC分类号： G01R31/28 , H01L21/66 , H01L21/82 , H03K17/693 , H03K19/00 , H03K19/003 , H03K19/0185 , H03K19/173
CPC分类号： H03K17/693 , H03K19/00361 , H03K19/018585
摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.
摘要翻译：具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号被披露。每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 以及多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;锁存器，连接到第一存储装置的输出端，用于存储信号以及连接到所述锁存器的输出端的第二多路复用器。这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试系统逻辑。控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。

7. 发明授权

US07880497B2 Fault tolerant integrated circuit architecture 有权
标题翻译：容错集成电路架构
公开(公告)号：US07880497B2
公开(公告)日：2011-02-01
申请号：US12463040
申请日：2009-05-08
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

8. 发明授权

US07705624B2 Fault tolerant integrated circuit architecture 失效
标题翻译：容错集成电路架构
公开(公告)号：US07705624B2
公开(公告)日：2010-04-27
申请号：US12193015
申请日：2008-08-17
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

9. 发明申请

US20090134906A1 Resilient Integrated Circuit Architecture 有权
标题翻译：弹性集成电路架构
公开(公告)号：US20090134906A1
公开(公告)日：2009-05-28
申请号：US12193014
申请日：2008-08-17
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
IPC分类号： H03K19/003 , H03K19/173
CPC分类号： H03K19/17752 , H03K19/17736 , H03K19/17756 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

10. 发明授权

US06708325B2 Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic 失效
标题翻译：将高级编程语言编译成具有多重可重构逻辑的嵌入式微处理器的方法
公开(公告)号：US06708325B2
公开(公告)日：2004-03-16
申请号：US09446758
申请日：2000-05-31
申请人： Laurence H. Cooke , Christopher E. Phillips , Dale Wong
发明人： Laurence H. Cooke , Christopher E. Phillips , Dale Wong
IPC分类号： G06F944
CPC分类号： G06F17/5045 , G06F8/4441 , G06F8/447 , G06F8/451 , G06F9/30181
摘要： A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit (ASIC), to improve overall performance. The critical blocks of logic are transformed into new equivalent logic with maximal data parallelism. The parallelized logic is then translated into a Boolean gate representation, which is suitable for implementation on an ASIC. The ASIC may be coupled with a generic microprocessor via custom instruction for the microprocessor. The original computer program is then compiled into object code with the new expanded target instruction set.
摘要翻译：一种用于将以高级编程语言编写的计算机程序自动编译成中间数据结构的计算机实现的方法。分析数据结构以识别关键的逻辑块，其可以被实现为专用集成电路（ASIC），以提高整体性能。逻辑的关键块被转换成具有最大数据并行性的新的等效逻辑。然后将并行化逻辑转换为布尔门表示，适用于ASIC上的实现。 ASIC可以通过微处理器的定制指令与通用微处理器耦合。然后将原始计算机程序用新的扩展目标指令集编译成目标代码。

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