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1. 发明授权

US08446166B2 Resilient integrated circuit architecture 失效
公开(公告)号：US08446166B2
公开(公告)日：2013-05-21
申请号：US13160345
申请日：2011-06-14
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

2. 发明授权

US08384416B2 Fault tolerant integrated circuit architecture 失效
公开(公告)号：US08384416B2
公开(公告)日：2013-02-26
申请号：US12977319
申请日：2010-12-23
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

3. 发明申请

US20120098565A1 Resilient Integrated Circuit Architecture 失效
标题翻译：弹性集成电路架构
公开(公告)号：US20120098565A1
公开(公告)日：2012-04-26
申请号：US13160345
申请日：2011-06-14
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003 , H03K19/177
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

4. 发明授权

US08067954B2 Fault tolerant integrated circuit architecture 失效
公开(公告)号：US08067954B2
公开(公告)日：2011-11-29
申请号：US12718986
申请日：2010-03-07
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

5. 发明申请

US20100244889A1 Resilient Integrated Circuit Architecture 失效
标题翻译：弹性集成电路架构
公开(公告)号：US20100244889A1
公开(公告)日：2010-09-30
申请号：US12567785
申请日：2009-09-27
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

6. 发明授权

US06333641B1 Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array 有权
标题翻译：用于在可编程门阵列内动态地定义可变大小的自主子阵列的装置和方法
公开(公告)号：US06333641B1
公开(公告)日：2001-12-25
申请号：US09565651
申请日：2000-05-05
申请人： Stephen L. Wasson
发明人： Stephen L. Wasson
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17796
摘要： A programmable logic device includes an array of logic modules. A standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, links the array of logic modules. An omniversal bus is positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable size attached to the omniversal bus.
摘要翻译：可编程逻辑器件包括一组逻辑模块。标准互连网格，具有垂直路由线，水平路由线路和本地路由线路，链接逻辑模块阵列。无线电总线位于逻辑模块阵列上。逻辑模块阵列包括到全能总线的选择性链路，使得全能总线动态地建立连接到全能总线的可变大小的逻辑模块的自主子阵列。

7. 发明授权

US08456191B2 Data-driven integrated circuit architecture 失效
标题翻译：数据驱动集成电路架构
公开(公告)号：US08456191B2
公开(公告)日：2013-06-04
申请号：US13216193
申请日：2011-08-23
申请人： Steven Hennick Kelem , Brian A. Box , John M. Rudosky , Stephen L. Wasson
发明人： Steven Hennick Kelem , Brian A. Box , John M. Rudosky , Stephen L. Wasson
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/173 , G06F9/3897 , G06F11/1423 , G06F11/1428 , G06F15/7867 , H03K19/007 , H03K19/17756
摘要： The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.
摘要翻译：示例性实施例提供可重构集成电路架构，其包括：可配置用于多个数据操作的可配置电路元件，每个数据操作对应于多个上下文的上下文; 多个输入队列; 多个输出队列; 一个或多个配置和控制寄存器，用于为多个上下文的每个上下文存储指定至少一个数据输入队列和至少一个数据输出队列的多个配置位，运行状态位和多个位; 以及耦合到所述可配置电路元件和所述一个或多个配置和控制寄存器的元件控制器，所述元件控制器允许在上下文指定的数据输入中输入数据到达时加载上下文配置和执行数据操作上下文运行状态被启用并且上下文指定的数据输出队列具有接受输出数据的状态时的队列。

8. 发明申请

US20120146685A1 Fault Tolerant Integrated Circuit Architecture 失效
标题翻译：容错集成电路架构
公开(公告)号：US20120146685A1
公开(公告)日：2012-06-14
申请号：US13276180
申请日：2011-10-18
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路，从而提供IC继续相同的功能，尽管存在缺陷可能在操作过程中出现。

9. 发明申请

US20120126850A1 Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules 失效
标题翻译：具有单位延迟模块的分级可扩展可重构集成电路架构
公开(公告)号：US20120126850A1
公开(公告)日：2012-05-24
申请号：US13216182
申请日：2011-08-23
申请人： Stephen L. Wasson , Brian A. Box , John M. Rudosky , Steven Hennick Kelem
发明人： Stephen L. Wasson , Brian A. Box , John M. Rudosky , Steven Hennick Kelem
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G06F9/3897 , G06F11/1423 , G06F11/1428 , G06F15/7867 , H03K19/007 , H03K19/17756
摘要： The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC.
摘要翻译：示例性实施例提供了可重新配置的集成电路架构，其具有在每个区域内和区域之间的数据操作和数据字传输的预定的单位定时增量（或延迟），其独立于应用程序布局和路由。示例性IC包括多个电路区域，每个区域包括：多个复合电路元件，多个集群队列和全互连总线。每个复合电路元件包括：可配置电路元件电路和元件接口和控制电路，元件接口和控制电路包括输入队列和输出队列。每个群集队列包括具有输入队列和输出队列的元素接口和控制。整个互连总线将区域内的每个输出队列与区域内的每个输入队列耦合。由复合电路元件执行的任何数据操作，通过群集队列传输的任何数据字以及通过第一全互连总线进行的任何数据字传输都是在预定的单位时间延迟内完成的，该单位时间延迟独立于应用程序布局和应用数据路由可重构IC。

10. 发明授权

US07812629B2 Resilient integrated circuit architecture 有权
标题翻译：弹性集成电路架构
公开(公告)号：US07812629B2
公开(公告)日：2010-10-12
申请号：US12193014
申请日：2008-08-17
申请人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
发明人： Steven Hennick Kelem , Jaime C. Cummins , John L. Watson , Robert Plunkett , Stephen L. Wasson , Brian A. Box , Enno Wein , Charles A. Furciniti , Christopher E. Phillips
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17752 , H03K19/17736 , H03K19/17756 , H03K19/17764
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
摘要翻译：示例性实施例提供了一种弹性集成电路。示例性IC包括多个复合电路元件，状态机元件（SME）和多个通信元件。每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件，并且其可以是可配置的。状态机元件基于元素类型分配各种功能，例如将第一配置分配给第一元素类型，将第二配置分配给第二元素类型，以及为相应的分配提供第一数据链接。响应于故障或故障的检测，状态机元件将第一配置重新分配给另一个复合电路元件，并创建用于执行相同功能的第二数据链路。分配，路由，故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性，从而尽可能在运行过程中出现缺陷，使IC能够继续相同的功能。

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