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    • 1. 发明授权
    • Data-driven integrated circuit architecture
    • 数据驱动集成电路架构
    • US08456191B2
    • 2013-06-04
    • US13216193
    • 2011-08-23
    • Steven Hennick KelemBrian A. BoxJohn M. RudoskyStephen L. Wasson
    • Steven Hennick KelemBrian A. BoxJohn M. RudoskyStephen L. Wasson
    • G06F7/38H03K19/177
    • H03K19/173G06F9/3897G06F11/1423G06F11/1428G06F15/7867H03K19/007H03K19/17756
    • The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data.
    • 示例性实施例提供可重构集成电路架构,其包括:可配置用于多个数据操作的可配置电路元件,每个数据操作对应于多个上下文的上下文; 多个输入队列; 多个输出队列; 一个或多个配置和控制寄存器,用于为多个上下文的每个上下文存储指定至少一个数据输入队列和至少一个数据输出队列的多个配置位,运行状态位和多个位; 以及耦合到所述可配置电路元件和所述一个或多个配置和控制寄存器的元件控制器,所述元件控制器允许在上下文指定的数据输入中输入数据到达时加载上下文配置和执行数据操作 上下文运行状态被启用并且上下文指定的数据输出队列具有接受输出数据的状态时的队列。
    • 3. 发明申请
    • Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules
    • 具有单位延迟模块的分级可扩展可重构集成电路架构
    • US20120126850A1
    • 2012-05-24
    • US13216182
    • 2011-08-23
    • Stephen L. WassonBrian A. BoxJohn M. RudoskySteven Hennick Kelem
    • Stephen L. WassonBrian A. BoxJohn M. RudoskySteven Hennick Kelem
    • H03K19/173
    • H03K19/17748G06F9/3897G06F11/1423G06F11/1428G06F15/7867H03K19/007H03K19/17756
    • The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC.
    • 示例性实施例提供了可重新配置的集成电路架构,其具有在每个区域内和区域之间的数据操作和数据字传输的预定的单位定时增量(或延迟),其独立于应用程序布局和路由。 示例性IC包括多个电路区域,每个区域包括:多个复合电路元件,多个集群队列和全互连总线。 每个复合电路元件包括:可配置电路元件电路和元件接口和控制电路,元件接口和控制电路包括输入队列和输出队列。 每个群集队列包括具有输入队列和输出队列的元素接口和控制。 整个互连总线将区域内的每个输出队列与区域内的每个输入队列耦合。 由复合电路元件执行的任何数据操作,通过群集队列传输的任何数据字以及通过第一全互连总线进行的任何数据字传输都是在预定的单位时间延迟内完成的,该单位时间延迟独立于应用程序布局和应用数据路由 可重构IC。
    • 6. 发明申请
    • Resilient integrated circuit architecture
    • 弹性集成电路架构
    • US20070296459A1
    • 2007-12-27
    • US11471875
    • 2006-06-21
    • Steven Hennick KelemJaime C. CumminsJohn L. WatsonRobert PlunkettStephen L. WassonBrian A. BoxEnno WeinCharles A. Furciniti
    • Steven Hennick KelemJaime C. CumminsJohn L. WatsonRobert PlunkettStephen L. WassonBrian A. BoxEnno WeinCharles A. Furciniti
    • H03K19/173
    • H03K19/17752H03K19/17736H03K19/17756H03K19/17764
    • The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.
    • 示例性实施例提供了一种弹性集成电路。 示例性IC包括多个复合电路元件,状态机元件(SME)和多个通信元件。 每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件,并且其可以是可配置的。 状态机元件基于元素类型分配各种功能,例如将第一配置分配给第一元素类型,将第二配置分配给第二元素类型,以及为相应的分配提供第一数据链接。 响应于故障或故障的检测,状态机元件将第一配置重新分配给另一个复合电路元件,并创建用于执行相同功能的第二数据链路。 分配,路由,故障检测和重新分配以及数据重新路由可以实现多种程序和算法的实时性,从而尽可能在运行过程中出现缺陷,使IC能够继续相同的功能。
    • 8. 发明授权
    • Program binding system, method and software for a resilient integrated circuit architecture
    • 程序绑定系统,弹性集成电路架构的方法和软件
    • US08516427B2
    • 2013-08-20
    • US11765906
    • 2007-06-20
    • Steven Hennick Kelem
    • Steven Hennick Kelem
    • G06F17/50
    • G06F9/5083G06F9/4881G06F15/17362G06F15/7867G06F17/5077H03K19/003H03K19/007H03K19/173H03K19/17748H03K19/17764Y02D10/12Y02D10/13
    • The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.
    • 示例性实施例提供了用于弹性集成电路的程序装订器。 示例性IC包括多个复合电路元件,状态机元件(SME)和多个通信元件。 每个复合电路元件包括可以由元件类型变化的元件接口和所选择的电路元件,并且其可以是可配置的。 示例性程序绑定方法包括:将第一动作分配给具有第一类型的第一计算元件; 将第二动作分配给具有第二类型的第二计算元件; 以及通过所选择的通信元件在所述第一计算元件和所述第二计算元件之间建立第一数据路由。 在检测到复合电路元件或通信元件的故障的情况下,可以重新分配各种动作,建立新的数据路由。
    • 9. 发明授权
    • Multi-context configurable memory controller
    • 多上下文可配置内存控制器
    • US08407429B2
    • 2013-03-26
    • US13216203
    • 2011-08-23
    • John M. RudoskyStephen L. WassonBrian A. BoxSteven Hennick Kelem
    • John M. RudoskyStephen L. WassonBrian A. BoxSteven Hennick Kelem
    • G06F12/00H03K19/173
    • G06F3/0629G06F9/3897G06F15/7867H03K19/007H03K19/17752H03K19/17756H03K19/17796
    • The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output queues; at least one configuration and control register to store, for each context of a plurality of contexts, a plurality of configuration bits; a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts, the plurality of data operations comprising memory address generation, memory write operations, and memory read operations, the configurable circuit element comprising a plurality of configurable address generators; and an element controller, the element controller comprising a port arbitration circuit to arbitrate among a plurality of contexts having a ready-to-run status, and the element controller to allow concurrent execution of multiple data operations for multiple contexts having the ready-to-run status.
    • 示例性实施例提供了一种多上下文可配置存储器控制器,包括:包括多个输入队列和多个输出队列的输入 - 输出数据端口阵列; 至少一个配置和控制寄存器,用于为多个上下文的每个上下文存储多个配置位; 可配置用于多个数据操作的可配置电路元件,每个数据操作对应于多个上下文的上下文,所述多个数据操作包括存储器地址生成,存储器写入操作和存储器读取操作,所述可配置电路元件包括: 多个可配置的地址发生器; 以及元件控制器,所述元件控制器包括端口仲裁电路,以在具有准备运行状态的多个上下文之间进行仲裁,并且所述元件控制器允许并行执行多个上下文的多个数据操作, 运行状态。