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    • 3. 发明申请
    • ARRAY SUBSTRATE AND DISPLAY APPARATUS USING THE SAME
    • 使用相同的阵列基板和显示设备
    • US20130075728A1
    • 2013-03-28
    • US13402997
    • 2012-02-23
    • Chuan-Feng LiuChi-Ming WuChia-Jen Chang
    • Chuan-Feng LiuChi-Ming WuChia-Jen Chang
    • H01L29/786
    • H01L27/124H01L27/1214H01L27/1251H01L29/41733
    • An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.
    • 阵列基板包括限定像素结构的扫描线和数据线。 每个像素结构包括第一TFT,第二TFT和像素电极。 第一TFT包括连接到扫描线的第一栅极,设置在第一栅极上方并部分地与第一栅极重叠的第一源极和设置在第一栅极上方的第一漏极。 第一个源的一端连接到数据线。 第一漏极具有至少一个第一凹部,其中第一源部分地设置。 第二TFT包括连接到扫描线的第二栅极,设置在第二栅极上方并连接到第一漏极的第二源极,以及设置在第二栅极上方并部分地与第二栅极重叠的第二漏极。 第二源具有至少一个第二凹部,其中第二漏极部分地设置。 像素电极连接到第二漏极。
    • 5. 发明授权
    • Multi-channel thin film transistor structure
    • 多通道薄膜晶体管结构
    • US07531837B2
    • 2009-05-12
    • US11559489
    • 2006-11-14
    • Chuan-Feng Liu
    • Chuan-Feng Liu
    • H01L27/13
    • H01L29/78696
    • A multi-channel thin film transistor structure including a first conducting layer, an insulating layer, a semiconductor layer and a second conducting layer is provided. The first conducting layer formed on a substrate includes a gate electrode. The insulating layer covers the first conducting layer. The semiconductor layer formed on the insulating layer includes a plurality of semiconductor islands located above the gate electrode. The second conducting layer formed on the insulating layer and on the semiconductor layer includes a source electrode and a drain electrode. Each one of the semiconductor islands is coupled electrically with the source electrode at one end and coupled electrically with the drain electrode at the other end.
    • 提供了包括第一导电层,绝缘层,半导体层和第二导电层的多沟道薄膜晶体管结构。 形成在基板上的第一导电层包括栅电极。 绝缘层覆盖第一导电层。 形成在绝缘层上的半导体层包括位于栅电极上方的多个半导体岛。 形成在绝缘层和半导体层上的第二导电层包括源电极和漏电极。 半导体岛中的每一个在一端与源电极电连接并且在另一端与漏电极电连接。
    • 6. 发明授权
    • Thin film transistor array substrate and electronic ink display device
    • 薄膜晶体管阵列基板和电子墨水显示装置
    • US08115202B2
    • 2012-02-14
    • US11651663
    • 2007-01-10
    • Yu-Chen HsuChuan-Feng LiuChia-Hao Kuo
    • Yu-Chen HsuChuan-Feng LiuChia-Hao Kuo
    • H01L23/50H01L29/10
    • G09G3/006G09G3/344
    • A thin film transistor array substrate suitable for being applied in an electronic ink display device is provided. The thin film transistor array substrate includes a substrate, scan lines, data lines, thin film transistors, pixel electrodes and testing signal lines. The data lines and the scan lines are disposed and define a plurality of pixel regions on the substrate. Each thin film transistor is disposed in the respective pixel region and driven by the corresponding scan line and data line. In addition, each pixel electrode is disposed in respective pixel region and electrically connected to the thin film transistor corresponding thereto. Furthermore, the testing signal line connects to the scan lines and/or the data lines in series. The testing accuracy as well as the production yield of the electronic ink display device and the thin film transistor array substrate can be improved by the design of the aforementioned testing circuit.
    • 提供适用于电子墨水显示装置的薄膜晶体管阵列基板。 薄膜晶体管阵列基板包括基板,扫描线,数据线,薄膜晶体管,像素电极和测试信号线。 数据线和扫描线被布置并且在衬底上限定多个像素区域。 每个薄膜晶体管设置在相应的像素区域中并由相应的扫描线和数据线驱动。 此外,每个像素电极设置在相应的像素区域中并且电连接到与其对应的薄膜晶体管。 此外,测试信号线串联连接到扫描线和/或数据线。 通过上述测试电路的设计可以提高电子墨水显示装置和薄膜晶体管阵列基板的测试精度以及产量。
    • 7. 发明申请
    • Display Panel
    • 显示面板
    • US20110006661A1
    • 2011-01-13
    • US12632806
    • 2009-12-08
    • Chuan-Feng LiuYa-Rou ChenWei-Lun SuHeng-Hao ChangChi-Ming Wu
    • Chuan-Feng LiuYa-Rou ChenWei-Lun SuHeng-Hao ChangChi-Ming Wu
    • H01J1/46
    • H01J31/127H01J9/261H01J29/862
    • A display panel includes a first substrate, a display layer, a second substrate and a water-proofing frame. The first substrate has a view area and a ring-shaped through trench and includes a first base, a first metal layer, a gate-insulating layer, a second metal layer, a semiconductor layer, a bibulous insulating layer and a pixel-electrode layer. The gate-insulating layer is disposed between the first and the second metal layers. The bibulous insulating layer is disposed on the second metal layer and the gate-insulating layer. The ring-shaped through trench passes through the bibulous insulating layer and the part of the gate-insulating layer exposed by the second metal layer and surrounds the view area. The water-proofing frame is disposed at the ring-shaped through trench, connects the first substrate and the second substrate and encloses a wet-proof space between the first substrate and the second substrate. Besides, another display panel is also provided.
    • 显示面板包括第一基板,显示层,第二基板和防水框架。 第一基板具有视野区域和环形贯通沟槽,并且包括第一基底,第一金属层,栅极绝缘层,第二金属层,半导体层,吸水绝缘层和像素电极层 。 栅极绝缘层设置在第一和第二金属层之间。 吸水绝缘层设置在第二金属层和栅极绝缘层上。 环形贯通沟槽穿过吸水绝缘层和由第二金属层暴露的栅极绝缘层的一部分并且围绕视野区域。 防水框架设置在环形通孔处,连接第一基板和第二基板,并且在第一基板和第二基板之间包围防湿空间。 此外,还提供另一显示面板。
    • 8. 发明申请
    • ACTIVE DEVICE ARRAY SUBSTRATE
    • 主动设备阵列基板
    • US20100090715A1
    • 2010-04-15
    • US12325022
    • 2008-11-28
    • Heng-Hao CHANGChuan-Feng Liu
    • Heng-Hao CHANGChuan-Feng Liu
    • G01R31/28H05K7/02
    • G02F1/1362G02F1/13458G02F2001/136254G09G3/006
    • An active device array substrate has a display area and a peripheral circuit area and further includes a plurality of pixel units, a plurality of signal lines, a plurality of testing pads and a first dielectric layer. The pixel units are arranged in the display area in an array. The signal lines and the testing pads are arranged in the peripheral circuit area. The first dielectric layer covers the testing pads. A testing method of the active device array substrate is that firstly removing a part of the first dielectric layer to expose a testing pad(s) desired to electrically contact with a testing tool. In other words, before the testing, the testing pads are electrically insulated from the exterior to prevent the pixel units from the electrostatic charges damage and thus the circuit stability of the active device array substrate can be improved.
    • 有源器件阵列衬底具有显示区域和外围电路区域,并且还包括多个像素单元,多个信号线,多个测试焊盘和第一介电层。 像素单元被布置在阵列中的显示区域中。 信号线和测试垫布置在外围电路区域中。 第一介质层覆盖测试垫。 有源器件阵列衬底的测试方法是首先去除第一介电层的一部分以露出与测试工具电接触的测试焊盘。 换句话说,在测试之前,测试焊盘与外部电绝缘以防止像素单元免受静电电荷的损害,从而可以提高有源器件阵列衬底的电路稳定性。