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1. 发明授权

US08105851B1 Nitride film wet stripping 有权
标题翻译：氮化膜湿剥
公开(公告)号：US08105851B1
公开(公告)日：2012-01-31
申请号：US12889167
申请日：2010-09-23
申请人： Shao-Yen Ku , Chung-Ru Yang , Chi-Ming Yang
发明人： Shao-Yen Ku , Chung-Ru Yang , Chi-Ming Yang
IPC分类号： H01L21/66
CPC分类号： H01L21/31111 , H01L21/6708 , H01L21/67253
摘要： Provided is a method of removing a nitride material from a semiconductor wafer. The method includes monitoring a silicon concentration level in a chemical solution. The chemical solution may include a phosphoric acid. The method includes adjusting the silicon concentration level in response to the monitoring. The method includes heating the chemical solution. The method includes applying the heated chemical solution to a wafer surface in a manner so that a temperature of the heated chemical solution is within a predefined temperature range throughout the wafer surface. The method includes etching a nitride material of the wafer using the heated chemical solution.
摘要翻译：提供从半导体晶片去除氮化物材料的方法。该方法包括监测化学溶液中的硅浓度水平。化学溶液可以包括磷酸。该方法包括响应于监测调整硅浓度水平。该方法包括加热化学溶液。该方法包括将加热的化学溶液以使得加热的化学溶液的温度在整个晶片表面的预定温度范围内的方式施加到晶片表面。该方法包括使用加热的化学溶液蚀刻晶片的氮化物材料。

2. 发明授权

US08404546B2 Source/drain carbon implant and RTA anneal, pre-SiGe deposition 有权
标题翻译：源极/漏极碳植入物和RTA退火，SiGe沉积
公开(公告)号：US08404546B2
公开(公告)日：2013-03-26
申请号：US12904878
申请日：2010-10-14
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/265 , H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

3. 发明授权

US08188447B2 Field-by-field laser annealing and feed forward process control 有权
标题翻译：逐场激光退火和前馈过程控制
公开(公告)号：US08188447B2
公开(公告)日：2012-05-29
申请号：US12359682
申请日：2009-01-26
申请人： Chung-Ru Yang , Chyi Shyuan Chern , Soon Kang Huang
发明人： Chung-Ru Yang , Chyi Shyuan Chern , Soon Kang Huang
IPC分类号： A61N5/00 , G21G5/00
CPC分类号： H01L21/268 , H01L21/28185 , H01L22/14 , H01L22/20 , H01L22/34
摘要： A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.
摘要翻译：一种方法包括将半导体晶片分成多个管芯区域，产生半导体晶片的映射图，用激光扫描半导体晶片的多个管芯区域中的每一个，并且在扫描期间调整激光器的参数，基于由半导体晶片的映射图识别的管芯区域的值。基于每个单个管芯区域的第一测量来描绘管芯区域的地图。

4. 发明申请

US20110027955A1 Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition 有权
标题翻译：来源/排水碳植入物和RTA退火，前SiGe沉积
公开(公告)号：US20110027955A1
公开(公告)日：2011-02-03
申请号：US12904878
申请日：2010-10-14
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

5. 发明申请

US20100187444A1 FIELD-BY-FIELD LASER ANNEALING AND FEED FORWARD PROCESS CONTROL 有权
标题翻译：现场激光退火和进给前进过程控制
公开(公告)号：US20100187444A1
公开(公告)日：2010-07-29
申请号：US12359682
申请日：2009-01-26
申请人： Chung-Ru Yang , Chyi Shyuan Chern , Soon Kang Huang
发明人： Chung-Ru Yang , Chyi Shyuan Chern , Soon Kang Huang
IPC分类号： A61N5/00
CPC分类号： H01L21/268 , H01L21/28185 , H01L22/14 , H01L22/20 , H01L22/34
摘要： A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.
摘要翻译：一种方法包括将半导体晶片分成多个管芯区域，产生半导体晶片的映射图，用激光扫描半导体晶片的多个管芯区域中的每一个，并且在扫描期间调整激光器的参数，基于由半导体晶片的映射图识别的管芯区域的值。基于每个单个管芯区域的第一测量来描绘管芯区域的地图。

6. 发明授权

US08232114B2 RTP spike annealing for semiconductor substrate dopant activation 有权
标题翻译：用于半导体衬底掺杂剂激活的RTP尖峰退火
公开(公告)号：US08232114B2
公开(公告)日：2012-07-31
申请号：US12360437
申请日：2009-01-27
申请人： Chin-Ming Lin , Chung-Ru Yang , Chi-Ming Yang
发明人： Chin-Ming Lin , Chung-Ru Yang , Chi-Ming Yang
IPC分类号： H01L21/324 , C30B1/02
CPC分类号： H01L21/324 , H01L21/67115
摘要： A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength.
摘要翻译：半导体衬底具有多个有源器件图案。至少一些有源器件图案包括掺杂区域。衬底具有多个表面区域，包括有源器件图案和未图案化区域，对于近红外波长的光分别具有不同的反射率。在近红外波长处的最大反射率和近红外波长处的最小反射率之间确定第一差异。确定第二红外波长，对于该第二红外波长，最大反射率之间的最小反射率的第二差值实质上小于近红外波长处的第一差。使用提供第二波长的光的第二光源在衬底上进行快速热处理（RTP）尖峰退火掺杂剂激活步骤。

7. 发明申请

US20100190274A1 RTP SPIKE ANNEALING FOR SEMICONDUCTOR SUBSTRATE DOPANT ACTIVATION 有权
公开(公告)号：US20100190274A1
公开(公告)日：2010-07-29
申请号：US12360437
申请日：2009-01-27
申请人： Chin-Ming LIN , Chung-Ru Yang , Chi-Ming Yang
发明人： Chin-Ming LIN , Chung-Ru Yang , Chi-Ming Yang
IPC分类号： H01L21/02 , B05C11/00
CPC分类号： H01L21/324 , H01L21/67115
摘要： A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength.
摘要翻译：半导体衬底具有多个有源器件图案。至少一些有源器件图案包括掺杂区域。衬底具有多个表面区域，包括有源器件图案和未图案化区域，对于近红外波长的光分别具有不同的反射率。在近红外波长处的最大反射率和近红外波长处的最小反射率之间确定第一差异。确定第二红外波长，对于该第二红外波长，最大反射率之间的最小反射率的第二差值实质上小于近红外波长处的第一差。使用提供第二波长的光的第二光源在衬底上进行快速热处理（RTP）尖峰退火掺杂剂激活步骤。

8. 发明授权

US07838887B2 Source/drain carbon implant and RTA anneal, pre-SiGe deposition 有权
标题翻译：源极/漏极碳植入物和RTA退火，SiGe沉积
公开(公告)号：US07838887B2
公开(公告)日：2010-11-23
申请号：US12112507
申请日：2008-04-30
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

9. 发明申请

US20090273034A1 Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition 有权
标题翻译：来源/排水碳植入物和RTA退火，前SiGe沉积
公开(公告)号：US20090273034A1
公开(公告)日：2009-11-05
申请号：US12112507
申请日：2008-04-30
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

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