专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09341313B2 Gas hood for gas regulator 有权
标题翻译：气体调节器用气罩
公开(公告)号：US09341313B2
公开(公告)日：2016-05-17
申请号：US13528864
申请日：2012-06-21
申请人： Shih-Hsun Chang
发明人： Shih-Hsun Chang
IPC分类号： F17C13/10
CPC分类号： F17C13/10 , F17C2205/0176 , F17C2205/0338 , F17C2260/032 , F17C2270/0518 , Y10T137/7043
摘要： A gas hood for a gas regulator comprises a housing for covering a gas regulator, an opening for receiving the gas regulator and semi-sealing the space between the housing and the gas regulator, and a gas inlet for constantly introducing gas into the space, wherein parts of the gas escapes from the opening so that the space can maintain a micro-positive pressure.
摘要翻译：用于气体调节器的气体罩包括用于覆盖气体调节器的壳体，用于接收气体调节器的开口和半密封壳体和气体调节器之间的空间，以及用于不断地将气体引入空间的气体入口，其中气体的一部分从开口逸出，使得空间能够保持微正压。

2. 发明授权

US08737062B2 Handheld electronic device 有权
标题翻译：手持电子设备
公开(公告)号：US08737062B2
公开(公告)日：2014-05-27
申请号：US13303129
申请日：2011-11-22
申请人： Chih-Kuang Wang , Tsung-Yuan Ou , Li-Hsun Chang
发明人： Chih-Kuang Wang , Tsung-Yuan Ou , Li-Hsun Chang
IPC分类号： H05K5/00 , H05K7/00 , G06F1/16
CPC分类号： H04M1/0249 , H04M2250/22
摘要： A handheld electronic device including a lower housing, an upper housing, a touch panel, a display module, a partition, position posts, cushions, and an actuator is provided. The upper housing is above and separated from the lower housing. The touch panel is at an opening of the upper housing and connects with the upper housing. The display module is disposed in the upper housing and connected with the lower housing. The partition is between the display module and the lower housing and connected to the upper housing. The partition has position holes. The position posts are located in their corresponding position holes and connected with the display module. The cushions are located between the corresponding position post and the position hole. The actuator is disposed between the display module and the upper housing to force the upper housing to shift relative to the display module and the lower housing.
摘要翻译：提供了包括下壳体，上壳体，触摸面板，显示模块，分隔件，位置柱，衬垫和致动器的手持式电子设备。上壳体在下壳体之上并与下壳体分离。触摸面板位于上壳体的开口处并与上壳体连接。显示模块设置在上壳体中并与下壳体连接。分隔件位于显示模块和下壳体之间，并连接到上壳体。分区有定位孔。位置柱位于其相应的位置孔中并与显示模块连接。垫子位于相应的位置柱和位置孔之间。致动器设置在显示模块和上壳体之间，以迫使上壳体相对于显示模块和下壳体移动。

3. 发明授权

US08692742B2 Pixel driving circuit with multiple current paths in a light emitting display panel 有权
标题翻译：在发光显示面板中具有多个电流路径的像素驱动电路
公开(公告)号：US08692742B2
公开(公告)日：2014-04-08
申请号：US12584221
申请日：2009-09-01
申请人： Tsung-Ting Tsai , Lee-Hsun Chang
发明人： Tsung-Ting Tsai , Lee-Hsun Chang
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2300/0426 , G09G2300/0439 , G09G2300/0465 , G09G2300/0842 , G09G2300/0852 , G09G2320/0223 , G09G2320/0233 , G09G2330/02 , H01L27/326
摘要： A display panel has a plurality of OLED pixels arranged in rows and columns. The pixel driving circuit has two or more current paths through a plurality of switching elements for providing the necessary current to the OLEDs in a pixel. The control end of each switching element is connected to the control end of the other switching elements, but each switching element has a separate power source which can be separately adjustable. In some embodiments, in a pixel or sub-pixel, one switching element is located at one end and one switching element is located at the other end of a pixel length, and each pixel is adjacent to a first power source line and a second power source line along the pixel length for separately providing the electrical power to two switching elements.
摘要翻译：显示面板具有以行和列排列的多个OLED像素。像素驱动电路具有穿过多个开关元件的两个或多个电流路径，用于向像素中的OLED提供必要的电流。每个开关元件的控制端连接到其他开关元件的控制端，但是每个开关元件具有可单独调节的单独的电源。在一些实施例中，在像素或子像素中，一个开关元件位于一端，一个开关元件位于像素长度的另一端，并且每个像素与第一电源线和第二电源相邻源极线沿像素长度分开提供电力到两个开关元件。

4. 发明授权

US08284377B2 Display device and repairing method therefor 有权
标题翻译：显示装置及其修理方法
公开(公告)号：US08284377B2
公开(公告)日：2012-10-09
申请号：US12553973
申请日：2009-09-03
申请人： Je-Hao Hsu , Wen-Pin Chen , Chiu-Mei Yu , Lee-Hsun Chang
发明人： Je-Hao Hsu , Wen-Pin Chen , Chiu-Mei Yu , Lee-Hsun Chang
IPC分类号： G02F1/1333 , G02F1/13 , G02F1/1345 , G06F3/038 , G09G3/36
CPC分类号： G02F1/136259 , G09G3/3677 , G09G2330/08
摘要： In a display device and a repairing method therefor, the display device includes a gate line and two gate-on-array circuits arranged at two sides thereof. Each of the gate-on-array circuits includes a stage coupled to the gate line. Each the stage includes a transistor and a repair circuit. The first source/drain electrode of the transistor is coupled to the gate line, and the second source/drain electrode of the transistor is coupled to receive a clock pulse signal. The repair circuit includes a first terminal coupled to the gate electrode of the transistor, a second terminal coupled to a predetermined potential, and at least one control terminal adapted to receive at least one repair signal to pull the potential on the gate electrode of the transistor to the predetermined potential. The transistor maintains at off-state when the at least one repair signal is supplied to the repair circuit.
摘要翻译：在显示装置及其修复方法中，显示装置包括设置在其两侧的栅极线和两个栅极阵列电路。栅阵列电路中的每一个包括耦合到栅极线的级。每个级包括晶体管和修复电路。晶体管的第一源/漏电极耦合到栅极线，并且晶体管的第二源极/漏极电极被耦合以接收时钟脉冲信号。修复电路包括耦合到晶体管的栅电极的第一端子，耦合到预定电位的第二端子，以及至少一个控制端子，适于接收至少一个修复信号以拉动晶体管的栅电极上的电位达到预定的电位。当至少一个修复信号被提供给修复电路时，晶体管保持断开状态。

5. 发明申请

US20110169798A1 Active Matrix Organic Light Emitting Diode (OLED) Display, Pixel Circuit and Data Current Writing Method Thereof 有权
标题翻译：有源矩阵有机发光二极管（OLED）显示器，像素电路和数据电流写入方法
公开(公告)号：US20110169798A1
公开(公告)日：2011-07-14
申请号：US12684902
申请日：2010-01-09
申请人： Chia-Yu LEE , Lee-Hsun CHANG , Tze-Chien TSAI
发明人： Chia-Yu LEE , Lee-Hsun CHANG , Tze-Chien TSAI
IPC分类号： G06F3/038
CPC分类号： G09G3/3233 , G09G2300/0842 , G09G2320/0219 , G09G2320/0295 , G09G2320/043
摘要： An exemplary active matrix organic light emitting diode (OLED) display includes a data line, a current sensing line, a power line and a plurality of pixels all electrically coupled to the data line, the current sensing line and the power line. During a data current is writing to a selected one of the pixels, the selected pixel draws a current from the current sensing line, and the data line supplies a particular data voltage to the selected pixel according to the drawn current from the current sensing line until the drawn current matched with the data current; the other non-selected pixels draw currents from the power line for light-emission. Moreover, a pixel circuit and a data current writing method adapted for the above-mentioned active matrix OLED display also are provided.
摘要翻译：示例性的有源矩阵有机发光二极管（OLED）显示器包括全部电耦合到数据线，电流感测线和电力线的数据线，电流感测线，电力线和多个像素。在数据电流正在写入所选择的一个像素的过程中，所选择的像素从电流感测线吸取电流，并且数据线根据从电流感测线引出的电流向所选择的像素提供特定数据电压，直到绘制电流与数据电流匹配; 其他未选择的像素从电力线抽出电流用于发光。此外，还提供了适用于上述有源矩阵OLED显示器的像素电路和数据电流写入方法。

6. 发明申请

US20110049703A1 Flip-Chip Package Structure 审中-公开
标题翻译：倒装芯片封装结构
公开(公告)号：US20110049703A1
公开(公告)日：2011-03-03
申请号：US12547475
申请日：2009-08-25
申请人： Jun-Chung Hsu , Shuo-Hsun Chang
发明人： Jun-Chung Hsu , Shuo-Hsun Chang
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.
摘要翻译：提供了倒装芯片（FC）封装结构。 FC封装结构包括基板，芯片，多个铜平台，多个铜凸块，镀层，电路层和焊料掩模层。铜凸块设置在基板上。铜平台堆叠在铜凸块上。电镀层覆盖铜凸块和铜平台，用于与配置在芯片底部的芯片脚垫接触。 FC封装结构不需要预留用于引线接合的空间，从而节省了基板的面积。铜平台堆叠在铜凸块上，并且高于电路图案层。因此，芯片被堵塞，并且芯片和基板之间的间隙扩大，从而防止在填充包层材料时配置空隙的风险并提高包装产量。

7. 发明授权

US07838887B2 Source/drain carbon implant and RTA anneal, pre-SiGe deposition 有权
标题翻译：源极/漏极碳植入物和RTA退火，SiGe沉积
公开(公告)号：US07838887B2
公开(公告)日：2010-11-23
申请号：US12112507
申请日：2008-04-30
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

8. 发明授权

US07812413B2 MOSFET devices and methods for making them 有权
标题翻译： MOSFET器件及其制造方法
公开(公告)号：US07812413B2
公开(公告)日：2010-10-12
申请号：US12233286
申请日：2008-09-18
申请人： Shih-Hsun Chang , Lars-Ake Ragnarsson
发明人： Shih-Hsun Chang , Lars-Ake Ragnarsson
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L29/49 , H01L29/51
CPC分类号： H01L29/517 , H01L21/28035 , H01L21/28194 , H01L21/823857 , H01L29/4916 , H01L29/513
摘要： A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium.
摘要翻译：公开了一种半导体器件。该器件包括第一MOSFET晶体管。晶体管包括衬底，在衬底上的第一高k电介质层，在第一高k电介质上的第一介电覆盖层，以及由第一掺杂水平和第一导电类型的半导体材料制成的第一栅电极在第一介电覆盖层上。第一介电覆盖层包括钪。

9. 发明申请

US20100054392A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100054392A1
公开(公告)日：2010-03-04
申请号：US12429018
申请日：2009-04-23
申请人： Wen-pin Chen , Lee-hsun Chang , Je-hao Hsu
发明人： Wen-pin Chen , Lee-hsun Chang , Je-hao Hsu
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G2310/0286 , G09G2320/0266
摘要： A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.
摘要翻译：移位寄存器包括彼此串联连接的多个级。每个级包括上拉电路，上拉驱动电路和下拉电路。耦合到第一时钟信号的上拉电路用于提供输出信号。上拉驱动电路包括控制电路和第一晶体管。控制电路具有耦合到前一级的栅极和耦合到第二时钟信号的漏极。第一晶体管包括耦合到控制电路的源极的栅极，耦合到前一级的驱动端的漏极和耦合到第一输入端的源极。下拉电路拉低第一个输入端的电压。

10. 发明申请

US20090273034A1 Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition 有权
标题翻译：来源/排水碳植入物和RTA退火，前SiGe沉积
公开(公告)号：US20090273034A1
公开(公告)日：2009-11-05
申请号：US12112507
申请日：2008-04-30
申请人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
发明人： Wei-Yen Woon , Chun-Feng Nieh , Ching-Yi Chen , Hsun Chang , Chung-Ru Yang , Li-Te S. Lin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.
摘要翻译：公开了一种半导体器件系统，结构和制造源极/漏极的方法，以阻止掺杂剂从胁迫源向外扩散。示例性实施例包括半导体衬底，器件和方法，用于延迟源极/漏极区域中的侧向掺杂剂扩散。半导体衬底设置有栅极结构，栅极结构的相对侧上具有源极和漏极。在源极和漏极的一部分中蚀刻凹入的区域。掺杂的应激物嵌入到凹陷区域中。势垒掺杂剂掺入源极和漏极的剩余部分中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式