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1. 发明申请

US20140217945A1 CONTROL TECHNIQUES FOR MOTOR DRIVEN SYSTEMS UTILIZING BACK-EMF MEASUREMENT TECHNIQUES 有权
标题翻译：利用反电动势测量技术的电机驱动系统的控制技术
公开(公告)号：US20140217945A1
公开(公告)日：2014-08-07
申请号：US13760622
申请日：2013-02-06
申请人： Alan Patrick Cahill , Gary Casey , John A. Cleary , Eoin Edward English , Christian Jimenez , Javier Calpe Maravilla , Colin G. Lyden , Thomas F. Roche
发明人： Alan Patrick Cahill , Gary Casey , John A. Cleary , Eoin Edward English , Christian Jimenez , Javier Calpe Maravilla , Colin G. Lyden , Thomas F. Roche
IPC分类号： G01H13/00 , H02P31/00
CPC分类号： G01H13/00 , H02P25/028 , H02P25/034
摘要： A method and apparatus for automatic resonance detection is disclosed for a motor-driven mechanical system such as a voice coil motor (VCM) in which a resonance detector and driver are provided. The automatic resonance detector may be implemented on the same integrated circuit as the driver, and dynamically determines the natural resonant frequency of the VCM driven by the driver. The resonant frequency is determined by measuring the back electromotive force (BEMF) of the VCM, detecting the slope of the BEMF signal, and determining the resonant frequency from the slope of the BEMF signal.
摘要翻译：公开了一种用于自动共振检测的方法和装置，用于诸如提供谐振检测器和驱动器的音圈电机（VCM）的电动机械系统。自动共振检测器可以在与驱动器相同的集成电路上实现，并且动态地确定由驱动器驱动的VCM的固有谐振频率。谐振频率通过测量VCM的反电动势（BEMF），检测BEMF信号的斜率以及从BEMF信号的斜率确定谐振频率来确定。

2. 发明申请

US20100176979A1 ANALOG TO DIGITAL CONVERTER 有权
标题翻译：模拟到数字转换器
公开(公告)号：US20100176979A1
公开(公告)日：2010-07-15
申请号：US12534392
申请日：2009-08-03
申请人： Christopher Peter HURRELL , Colin G. LYDEN , Ronald A. KAPUSTA
发明人： Christopher Peter HURRELL , Colin G. LYDEN , Ronald A. KAPUSTA
IPC分类号： H03M1/12
CPC分类号： H03M1/0626 , H03M1/164 , H03M1/44 , H03M1/466
摘要： An analog to digital converter comprising an Nth analog to digital converter and an N+1th analog to digital converter arranged in series such that a residue signal from the Nth analog to digital converter is provided as an input to the N+1th analog to digital converter, characterised in that a bandwidth control means is provided in a signal path for the residue signal and the bandwidth control means is controlled so as to have a first bandwidth during a first period following generation of a conversion result from the Nth analog to digital converter, and a second bandwidth less than the first bandwidth in a second period following the first period.
摘要翻译：一种包括第N模数转换器和N + 1模数转换器的模数转换器，其串联布置，使得来自第N模数转换器的残留信号被提供给第N + 1模数转换器其特征在于，在残留信号的信号路径中提供带宽控制装置，并且在产生来自第N模拟数字转换器的转换结果之后的第一周期期间，控制带宽控制装置以具有第一带宽，以及在所述第一周期之后的第二周期中小于所述第一带宽的第二带宽。

3. 发明授权

US07193545B2 Differential front-end continuous-time sigma-delta ADC using chopper stabilization 有权
标题翻译：差分前端连续时间Σ-ΔADC使用斩波稳定
公开(公告)号：US07193545B2
公开(公告)日：2007-03-20
申请号：US11228113
申请日：2005-09-16
申请人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
发明人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/332 , H03M3/424 , H03M3/454
摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.
摘要翻译：多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。积分放大器也可以斩波稳定。

4. 发明授权

US07113116B2 Sample and hold apparatus 有权
标题翻译：采样和保持设备
公开(公告)号：US07113116B2
公开(公告)日：2006-09-26
申请号：US11045672
申请日：2005-01-26
申请人： Robert J. Brewer , Colin G. Lyden , Michael C. W. Coln
发明人： Robert J. Brewer , Colin G. Lyden , Michael C. W. Coln
IPC分类号： H03M1/00
CPC分类号： G11C27/026 , G11C27/024
摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.
摘要翻译：提供一种采集和平均电路，其中在采样相位期间，采样块4和6中的电容器顺序地连接到输入信号以对其进行采样，然后被隔离以保持样本。然后将电容器连接到组合/平均布置，使得形成样本值的平均值。

5. 发明申请

US20190242729A1 MEASUREMENT SYSTEM 审中-公开
公开(公告)号：US20190242729A1
公开(公告)日：2019-08-08
申请号：US16262579
申请日：2019-01-30
申请人： Claire Croke , Aine McCarthy , Adrian Sherry , Giovanni C. Dotta , Dan O'Donovan , Sean Wilson , Mary McCarthy , Colin G. Lyden , Fiona Treacy , Michael Byrne
发明人： Claire Croke , Aine McCarthy , Adrian Sherry , Giovanni C. Dotta , Dan O'Donovan , Sean Wilson , Mary McCarthy , Colin G. Lyden , Fiona Treacy , Michael Byrne
IPC分类号： G01D18/00
CPC分类号： G01D18/00
摘要： Various examples are directed to systems and methods for managing a sensor. A measurement system may receive, from a host device, a first register map describing a first configuration of a measurement system. The first configuration may be associated with a first sensor. The measurement system may compare the first register map to an error rule set indicating inconsistent register map arrangements. After comparing the first register map to the error rule set, the measurement system may configure a switch matrix of the measurement system to sample the first sensor according to the first configuration of the measurement TO system. The measurement system may receive a plurality of samples from a first sensor and generate first digital measurement data based at least in part on the plurality of samples.

6. 发明申请

US20130293294A1 PROGRAMMABLE GAIN AMPLIFIER WITH AMPLIFIER COMMON MODE SAMPLING SYSTEM 有权
标题翻译：具有放大器通用模式采样系统的可编程增益放大器
公开(公告)号：US20130293294A1
公开(公告)日：2013-11-07
申请号：US13592074
申请日：2012-08-22
申请人： Colin G. LYDEN , Roberto S. MAURINO , Damien J. MCCARTNEY
发明人： Colin G. LYDEN , Roberto S. MAURINO , Damien J. MCCARTNEY
IPC分类号： H03G3/20
CPC分类号： H03G3/008
摘要： A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.
摘要翻译：可编程增益放大器（“PGA”）可以包括差分放大器，一对输入电容器，在放大器的反馈配置中提供的一对反馈电容器，设置在PGA输入端的第一斩波电路， PGA和设置在PGA输出端的第二斩波电路。 PGA还可以包括在采样阶段对输入电容器两端的电压进行采样的电路系统。采样电压可以对应于PGA的输入信号的共模电压与差分放大器的共模电压之间的差。因此，当斩波电路工作时，采样电压在其他操作阶段确定放大器输入端的共模电压。

7. 发明申请

US20130207820A1 SIGMA DELTA MODULATOR WITH DITHER 有权
标题翻译： SIGMA DELTA调制器与DITHER
公开(公告)号：US20130207820A1
公开(公告)日：2013-08-15
申请号：US13715005
申请日：2012-12-14
申请人： Roberto S. MAURINO , Colin G. LYDEN
发明人： Roberto S. MAURINO , Colin G. LYDEN
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/328 , H03M3/422
摘要： A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.
摘要翻译： Σ-Δ调制器可以包括环路滤波器和被配置为接受环路滤波器的输出和抖动输入信号的加法器。加法器可以被进一步配置为将环路滤波器的输出和抖动输入信号组合成组合的输出信号。 Σ-Δ调制器还可以包括量化器，其被配置为接受来自加法器的组合输出信号，并将组合信号量化为量化器输出信号。 Σ-Δ调制器还可以包括：第一减法器，被配置为接受量化器输出信号，并从量化器输出信号中减去抖动输入信号。

8. 发明申请

US20090115522A1 Low power, low noise amplifier system 有权
标题翻译：低功耗，低噪声放大器系统
公开(公告)号：US20090115522A1
公开(公告)日：2009-05-07
申请号：US12283511
申请日：2008-09-12
申请人： Colin G. Lyden , Christian S. Birk , Tomas Tansley
发明人： Colin G. Lyden , Christian S. Birk , Tomas Tansley
IPC分类号： H03F3/45 , H03F1/38
CPC分类号： H03F3/387 , H03F3/45475 , H03F2200/294 , H03F2203/45134 , H03F2203/45521 , H03F2203/45526
摘要： A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification of the low frequency differential inputs.
摘要翻译：低功率，低噪声放大器系统包括至少一个具有第一和第二差分输入端的放大器，第一和第二差分输出端并提供差分输出; 与第一和第二差分放大器输入端互连的第一和第二输入电容器; 分别包含与放大器差分输入和输出端互连的第一和第二反馈电容器的第一和第二反馈电路; 输入斩波器开关电路，用于接收低频差分输入并选择性地交替地将那些通过输入电容器的低频差分输入交换到放大器的差分输入端; 输出斩波开关，用于接收并选择性地与输入斩波开关电路同步地交替地交换放大器差分输出; 以及响应于交换的差分输出的低通滤波器，用于提供低频差分输入的低噪声，低功率放大。

9. 发明授权

US07205920B2 Continuous-time-sigma-delta DAC using chopper stabalization 有权
标题翻译：使用斩波稳定的连续时间 - Σ-ΔDAC
公开(公告)号：US07205920B2
公开(公告)日：2007-04-17
申请号：US11228114
申请日：2005-09-16
申请人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson , Atsushi Matamura , Andrew Abo
发明人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson , Atsushi Matamura , Andrew Abo
IPC分类号： H03M1/66
CPC分类号： H03M3/34 , H03M3/502
摘要： A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency. from where it can be removed by filtering downstream of the current-to-voltage converter.
摘要翻译： Σ-Δ数模转换器包括根据输入数字信号产生电流的当前数模转换器（IDAC）级。输出电流 - 电压转换器将产生的信号连续地转换成电压。在输出电流 - 电压转换器中使用的放大器是斩波稳定的。转换器可以是单位或多位。 IDAC级可以用一对分支来实现，第一分支包括第一偏置电流源和包括第二偏置电流源的第二分支。通过一组开关将偏置电流源连接到输出电流 - 电压转换器，可以对偏置电流源进行斩波稳定。开关将偏置电流源以第一配置和第二反向配置连接到输出电流 - 电压转换器。这将调制由偏置电流源提供的闪烁噪声到斩波频率。从那里可以通过对电流 - 电压转换器的下游进行滤波来去除。

10. 发明授权

US07095351B2 Digital-to-analog converter structures 有权
标题翻译：数模转换器结构
公开(公告)号：US07095351B2
公开(公告)日：2006-08-22
申请号：US11048374
申请日：2005-02-01
申请人： Patrick C. Kirby , Colin G. Lyden , Tudor M. Vinereanu
发明人： Patrick C. Kirby , Colin G. Lyden , Tudor M. Vinereanu
IPC分类号： H03M1/78 , H03M1/68
CPC分类号： H03M1/1057 , H03M1/785
摘要： A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.
摘要翻译：描述了DAC体系结构。该架构特别适用于提供基于数字输入字的模拟电压输出。该架构包括可分解成第一组件的电阻梯形配置，其适于转换输入字的下部，以及适于转换输入字的上部的第二组件。校准DAC，使得第一组件可用于在从第二组件选择特定段时调整第二组件的输出。

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