专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150117105A1 NONVOLATILE MEMORY DEVICE AND METHOD DETECTING DEFECTIVE WORD LINE 有权
标题翻译：非易失性存储器件和检测有缺陷的字线的方法
公开(公告)号：US20150117105A1
公开(公告)日：2015-04-30
申请号：US14476151
申请日：2014-09-03
申请人： BONG-KIL JUNG , DAESEOK BYEON
发明人： BONG-KIL JUNG , DAESEOK BYEON
IPC分类号： G11C16/34 , G11C16/14
CPC分类号： G11C16/3459 , G11C8/08 , G11C16/0483 , G11C29/025 , G11C2029/1202
摘要： The inventive concept relates to a nonvolatile memory device and a method of detecting a defective word line. The method includes executing a defective word line detection operation using a program/erase voltage applied to a selected word line, wherein the defective word line detection operation determines whether or not the selected word line is defective in relation to respective word line voltage responses for the first and second segments during execution of the program/erase operation.
摘要翻译：本发明构思涉及非易失性存储器件和检测缺陷字线的方法。该方法包括使用施加到所选字线的编程/擦除电压来执行有缺陷的字线检测操作，其中，缺陷字线检测操作确定所选择的字线是否相对于相应的字线电压响应有缺陷执行程序/擦除操作期间的第一和第二段。

2. 发明授权

US09666525B2 Three-dimensional semiconductor memory device 有权
公开(公告)号：US09666525B2
公开(公告)日：2017-05-30
申请号：US15201994
申请日：2016-07-05
申请人： Jeeyong Kim , Daeseok Byeon , Jung-Hwan Lee , Sanghoon Ahn
发明人： Jeeyong Kim , Daeseok Byeon , Jung-Hwan Lee , Sanghoon Ahn
IPC分类号： H01L29/792 , H01L23/522 , H01L27/1157 , H01L27/11582 , H01L23/528 , H01L27/11573
CPC分类号： H01L23/5226 , H01L21/7682 , H01L23/528 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2221/1047
摘要： Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.

3. 发明授权

US09842654B2 Nonvolatile memory device with improved reliability and operating speed 有权
公开(公告)号：US09842654B2
公开(公告)日：2017-12-12
申请号：US14996249
申请日：2016-01-15
申请人： Ji-Sang Lee , Donghun Kwak , Daeseok Byeon , Chiweon Yoon
发明人： Ji-Sang Lee , Donghun Kwak , Daeseok Byeon , Chiweon Yoon
IPC分类号： G11C11/34 , G11C16/10 , G11C16/26 , G11C16/04 , G11C16/24 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

4. 发明申请

US20170011799A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20170011799A1
公开(公告)日：2017-01-12
申请号：US14996249
申请日：2016-01-15
申请人： JI-SANG LEE , DONGHUN KWAK , DAESEOK BYEON , CHIWEON YOON
发明人： JI-SANG LEE , DONGHUN KWAK , DAESEOK BYEON , CHIWEON YOON
IPC分类号： G11C16/10 , G11C16/24 , G11C16/04 , G11C16/30 , G11C16/08 , G11C16/26
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
摘要翻译：非易失性存储器包括存储单元阵列，行解码器电路和页缓冲电路。行解码器电路响应于从外部设备接收到的写入命令，在第一预充电操作时，对连接到所选存储块的串选择晶体管的串选择线施加导通电压。页缓冲器电路响应于写入命令，在第一预充电操作下，连接到串选择晶体管的第一电压至位线，而不管加载数据如何，并施加第一电压和基于所加载的数据，在第二预充电操作中通过第二预充电电路对位线施加第二电压。在第一预充电操作期间，写数据被加载到页缓冲电路。

5. 发明授权

US09224495B2 Nonvolatile memory device and method detecting defective word line 有权
标题翻译：非易失性存储器件和方法检测有缺陷的字线
公开(公告)号：US09224495B2
公开(公告)日：2015-12-29
申请号：US14476151
申请日：2014-09-03
申请人： Bong-Kil Jung , Daeseok Byeon
发明人： Bong-Kil Jung , Daeseok Byeon
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C8/08 , G11C16/0483 , G11C29/025 , G11C2029/1202
摘要： The inventive concept relates to a nonvolatile memory device and a method of detecting a defective word line. The method includes executing a defective word line detection operation using a program/erase voltage applied to a selected word line, wherein the defective word line detection operation determines whether or not the selected word line is defective in relation to respective word line voltage responses for the first and second segments during execution of the program/erase operation.
摘要翻译：本发明构思涉及非易失性存储器件和检测缺陷字线的方法。该方法包括使用施加到所选字线的编程/擦除电压来执行有缺陷的字线检测操作，其中，缺陷字线检测操作确定所选择的字线是否相对于相应的字线电压响应有缺陷执行程序/擦除操作期间的第一和第二段。

6. 发明申请

US20170140824A1 NONVOLATILE MEMORY DEVICE INCLUDING MULTI-PLANE STRUCTURE 审中-公开
公开(公告)号：US20170140824A1
公开(公告)日：2017-05-18
申请号：US15342027
申请日：2016-11-02
申请人： DONGHUN KWAK , DAESEOK BYEON , CHIWEON YOON
发明人： DONGHUN KWAK , DAESEOK BYEON , CHIWEON YOON
IPC分类号： G11C16/08 , G11C16/04
CPC分类号： G11C16/08 , G11C16/0483
摘要： A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

7. 发明授权

US10056148B2 Nonvolatile memory device including multi-plane structure 有权
公开(公告)号：US10056148B2
公开(公告)日：2018-08-21
申请号：US15342027
申请日：2016-11-02
申请人： Donghun Kwak , Daeseok Byeon , Chiweon Yoon
发明人： Donghun Kwak , Daeseok Byeon , Chiweon Yoon
IPC分类号： G11C11/00 , G11C16/08 , G11C16/04
CPC分类号： G11C16/08 , G11C16/0483
摘要： A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

8. 发明申请

US20170062330A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20170062330A1
公开(公告)日：2017-03-02
申请号：US15201994
申请日：2016-07-05
申请人： Jeeyong KIM , Daeseok BYEON , Jung-Hwan LEE , Sanghoon AHN
发明人： Jeeyong KIM , Daeseok BYEON , Jung-Hwan LEE , Sanghoon AHN
IPC分类号： H01L23/522 , H01L23/528 , H01L27/115
CPC分类号： H01L23/5226 , H01L21/7682 , H01L23/528 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2221/1047
摘要： Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.
摘要翻译：可以提供能够提高可靠性的三维（3D）半导体存储器件。例如，其中垂直排列有多个存储单元串的三维（3D）存储器件可以包括衬底，交替多个层间电介质层（ILD）层和多个栅电极的堆叠结构， ILD层中的至少一个包括孔，穿过堆叠结构并电连接到衬底的垂直结构，以及堆叠结构和垂直结构之间的数据存储层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式