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1. 发明授权

US06467009B1 Configurable processor system unit 有权
标题翻译：可配置的处理器系统单元
公开(公告)号：US06467009B1
公开(公告)日：2002-10-15
申请号：US09172918
申请日：1998-10-14
申请人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
发明人： Steven Paul Winegarden , Bart Reynolds , Brian Fox , Jean-Didier Allegrucci , Sridhar Krishnamurthy , Danesh Tavana , Arye Ziklik , Andreas Papaliolios , Stanley S. Yang , Fung Fung Lee
IPC分类号： G06F100
CPC分类号： G06F15/7867 , G06F13/4217
摘要： The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
摘要翻译：可配置处理器系统包括处理器，内部系统总线和经由内部系统总线在单个集成电路上互连的可编程逻辑。

2. 发明授权

US5825202A Integrated circuit with field programmable and application specific logic areas 失效
公开(公告)号：US5825202A
公开(公告)日：1998-10-20
申请号：US721392
申请日：1996-09-26
申请人： Danesh Tavana , Wilson K. Yee , Stephen M. Trimberger
发明人： Danesh Tavana , Wilson K. Yee , Stephen M. Trimberger
IPC分类号： G06F15/78 , H03K19/177 , H03K7/38
CPC分类号： G06F15/7867 , H03K19/17704 , H03K19/17796
摘要： A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

3. 发明授权

US06212639B1 Encryption of configuration stream 有权
标题翻译：加密配置流
公开(公告)号：US06212639B1
公开(公告)日：2001-04-03
申请号：US09342336
申请日：1999-06-29
申请人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
发明人： Charles R. Erickson , Danesh Tavana , Victor A. Holen
IPC分类号： H04K100
CPC分类号： G06F21/57 , G06F12/1408 , G06F21/85
摘要： A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
摘要翻译：在可编程逻辑器件（PLD）和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。该方法包括以下步骤。将存储在存储设备中的加密配置数据发送到PLD。解密加密的配置数据以生成PLD中的配置数据的副本。使用配置数据的副本配置PLD。在一个实施例中，PLD将密钥发送到存储设备。在另一个实施例中，密钥分别输入到存储设备和PLD中，并且从未在PLD和存储设备之间传送密钥。在另一个实施例中，键仅输入到PLD中。密钥用于加密配置数据。

4. 发明授权

US5818255A Method and circuit for using a function generator of a programmable logic device to implement carry logic functions 失效
标题翻译：使用可编程逻辑器件的函数发生器来实现进位逻辑功能的方法和电路
公开(公告)号：US5818255A
公开(公告)日：1998-10-06
申请号：US536287
申请日：1995-09-29
申请人： Bernard J. New , Danesh Tavana
发明人： Bernard J. New , Danesh Tavana
IPC分类号： H03K19/173 , H03K7/38 , H03K19/21
CPC分类号： H03K19/1737
摘要： A carry logic circuit for a programmable logic device which uses a single function generator to create a carry propagate signal (P) and an output signal (S). The function generator includes a plurality of signal generation circuits, each of which is controlled by a first input signal (A) and a second input signal (B). One of the signal generation circuits is programmed to provide a desired carry propagate signal (P) in response to the first and second input signals (A,B). The carry propagate signal (P) is transmitted for use outside of the function generator to perform a carry propagation function for the carry logic circuit. The remaining signal generation circuits are programmed to generate one or more intermediate output signals in response to the first and second input signals (A,B). These intermediate output signals, in combination with carry propagate signal (P), are representative of the desired output signal (S). The function generator also includes a signal selection circuit which is coupled to the signal generation circuits. The signal selection circuit passes a signal which is selected from the group consisting of the carry propagate signal (P) and the intermediate output signals, thereby providing the output signal (S).
摘要翻译：一种用于可编程逻辑器件的进位逻辑电路，其使用单个函数发生器来产生进位传播信号（P）和输出信号（S）。功能发生器包括多个信号产生电路，每个信号产生电路由第一输入信号（A）和第二输入信号（B）控制。信号发生电路之一被编程为响应于第一和第二输入信号（A，B）提供期望的进位传播信号（P）。发送进位传播信号（P）以在功能发生器外部使用，以对进位逻辑电路执行进位传播功能。剩余的信号发生电路被编程为响应于第一和第二输入信号（A，B）产生一个或多个中间输出信号。这些中间输出信号与进位传播信号（P）相结合，代表期望的输出信号（S）。功能发生器还包括耦合到信号发生电路的信号选择电路。信号选择电路通过从由进位传播信号（P）和中间输出信号组成的组中选择的信号，从而提供输出信号（S）。

5. 发明授权

US6094065A Integrated circuit with field programmable and application specific logic areas 有权
标题翻译：具有现场可编程和专用逻辑区域的集成电路
公开(公告)号：US6094065A
公开(公告)日：2000-07-25
申请号：US176017
申请日：1998-10-20
申请人： Danesh Tavana , Wilson K. Yee , Stephen M. Trimberger
发明人： Danesh Tavana , Wilson K. Yee , Stephen M. Trimberger
IPC分类号： G06F15/78 , H03K19/177 , G06F7/38
CPC分类号： G06F15/7867 , H03K19/17704 , H03K19/17796
摘要： A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.
摘要翻译：一种异构集成电路器件，包括可编程地连接到集成电路上的掩模定义的应用专用逻辑区域（ASLA）的现场可编程门阵列（FPGA），从而为一种或另一种类型的均匀器件提供灵活的低成本替代。通过集成在单个单片IC上，用户从低成本和灵活性中获益。门阵列之间以及门阵列和输入/输出（I / O）电路之间的信号路由也被实现为掩模定义和可编程配置的互连的组合。

6. 发明授权

US5682107A FPGA architecture with repeatable tiles including routing matrices and logic matrices 失效
标题翻译：具有可重复瓦片的FPGA架构，包括路由矩阵和逻辑矩阵
公开(公告)号：US5682107A
公开(公告)日：1997-10-28
申请号：US618445
申请日：1996-03-19
申请人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
发明人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
摘要翻译： FPGA架构提供了通过路由矩阵直接连接到相邻逻辑元件和间接连接的逻辑元件。逻辑元件和路由矩阵的一部分被形成为瓦片的一部分，并且瓦片被连接以形成可选择尺寸的阵列。路由矩阵包括仅从一个瓦片连接到下一个瓦片的路由线路，以及通过几个瓦片或整个芯片延长更长距离的路由线路。这种组合是通过形成各个瓷砖来实现的，所有这些瓷砖都是相同的。

7. 发明授权

US5883525A FPGA architecture with repeatable titles including routing matrices and logic matrices 失效
标题翻译：具有可重复标题的FPGA架构，包括路由矩阵和逻辑矩阵
公开(公告)号：US5883525A
公开(公告)日：1999-03-16
申请号：US943890
申请日：1997-10-03
申请人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
发明人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
摘要翻译： FPGA架构提供了通过路由矩阵直接连接到相邻逻辑元件和间接连接的逻辑元件。逻辑元件和路由矩阵的一部分被形成为瓦片的一部分，并且瓦片被连接以形成可选择尺寸的阵列。路由矩阵包括仅从一个瓦片连接到下一个瓦片的路由线路，以及通过几个瓦片或整个芯片延长更长距离的路由线路。这种组合是通过形成各个瓷砖来实现的，所有这些瓷砖都是相同的。

8. 发明授权

US5635851A Read and writable data bus particularly for programmable logic devices 失效
标题翻译：读写数据总线，特别适用于可编程逻辑器件
公开(公告)号：US5635851A
公开(公告)日：1997-06-03
申请号：US595608
申请日：1996-02-02
申请人： Danesh Tavana
发明人： Danesh Tavana
IPC分类号： H03K17/687 , H03K17/693 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/6871 , H03K17/693 , H03K19/17704
摘要： A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.
摘要翻译：集成电路上的数据总线包括以环形布置的一系列选择器，每个选择器具有输出端子，使能端子，环形输入端子和数据输入端子。环形输入端子从环中的另一个选择器接收数据。数据输入端从数据源接收数据。输出端子将数据提供给环中下一个选择器的环形输入端。使能终端从数据源接收使能信号。选择器将其环形输入端子上的信号或其数据输入端子上的数据信号传播到下一个选择器。

9. 发明授权

US5504439A I/O interface cell for use with optional pad 失效
标题翻译： I / O接口单元用于可选焊盘
公开(公告)号：US5504439A
公开(公告)日：1996-04-02
申请号：US484064
申请日：1995-06-06
申请人： Danesh Tavana
发明人： Danesh Tavana
IPC分类号： H01L23/528 , H03K19/177
CPC分类号： H03K19/17744 , H01L23/528 , H03K19/17704 , H01L2924/0002 , H01L2924/3011
摘要： In a programmable integrated circuit device, a pad interface structure is provided in which the number of pads connected to the interface structure is selectively changed without redesigning the interface structure or redesigning the chip interior.
摘要翻译：在可编程集成电路器件中，提供焊盘接口结构，其中连接到接口结构的焊盘的数量被选择性地改变，而不重新设计接口结构或重新设计芯片内部。

10. 发明授权

US4698525A Buffered Miller current compensating circuit 失效
标题翻译：缓冲米勒电流补偿电路
公开(公告)号：US4698525A
公开(公告)日：1987-10-06
申请号：US804192
申请日：1985-12-03
申请人： Danesh Tavana , Sing Y. Wong
发明人： Danesh Tavana , Sing Y. Wong
IPC分类号： H03F3/20 , H03F3/30 , H03K17/04 , H03K17/60 , H03K19/013 , H03K19/088 , H03K19/08 , H03K3/33 , H03K19/003
CPC分类号： H03K19/0136 , H03K19/088
摘要： A TTL inverting output circuit (50) which uses the collector (65) of a parallel phase splitter transistor (Q11) where the voltage changes in phase with the circuit output signal Io to control an active circuit (70) which diverts charge from the base (23) of the output pull-down transistor (Q3).
摘要翻译：一种TTL反相输出电路（50），其使用并联分相晶体管（Q11）的集电极（65），其中电压与电路输出信号Io相变地控制有源电路（70），该有源电路将电荷从基极（Q3）的输出（23）。

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