专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090206952A1 DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS 有权
标题翻译：使用高频微调节器进行延时线路调节
公开(公告)号：US20090206952A1
公开(公告)日：2009-08-20
申请号：US12030946
申请日：2008-02-14
申请人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
发明人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
IPC分类号： H03H7/00
CPC分类号： H03H11/265
摘要： A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.
摘要翻译：稳定的延迟线装置包括耦合到节点的主调节器和耦合到节点的多个延迟分支，以通过主调节器接收到节点的电压输出。多个延迟分支中的每一个包括微调节器和延迟线。延迟线耦合到微调节器，使得在每个延迟分支处通过相应的微调节器局部去除未滤波的噪声。

2. 发明申请

US20060182215A1 Dynamic recalibration mechanism for elastic interface 失效
标题翻译：弹性界面的动态重新校准机制
公开(公告)号：US20060182215A1
公开(公告)日：2006-08-17
申请号：US11055865
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
发明人： Daniel Dreps , Frank Ferraiolo , Gary Peterson , Robert Reese
IPC分类号： H04L7/00
CPC分类号： H04L7/005 , G11C19/287 , H03K5/133 , H03K2005/00058 , H04L7/0338
摘要： A method and apparatus for de-skewing and aligning digital data received over and elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wraparound eye tracking.
摘要翻译：公开了一种用于使接收到的数字数据进行偏斜和对准的弹性接口总线的方法和装置。在接收到数据后，通过可编程延迟线发送。在可编程延迟线中，数据在数据眼图中的三个点进行采样。动态调整三个采样点，以最大化数据眼图的覆盖范围。在调整采样点以最佳地覆盖数据的眼图时，延迟数据从备用采样器采样，以防止在主采样器中的延迟调整时从功能采样器采样。在更换功能采样器的采样点时，从备用采样器进行采样可以减少在采样参数变化时采样功能采样器可能发生的毛刺。该方法和装置允许替代眼睛跟踪和环绕眼睛跟踪。

3. 发明申请

US20060181337A1 Digitally tunable high-current current reference with high PSRR 失效
标题翻译：数字可调高电流电流参考，高PSRR
公开(公告)号：US20060181337A1
公开(公告)日：2006-08-17
申请号：US11055840
申请日：2005-02-11
申请人： Daniel Dreps , Norman James , Hector Saenz
发明人： Daniel Dreps , Norman James , Hector Saenz
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple digitally selectable inputs are included in the current reference circuit and are coupled to the current source circuit. These inputs are used to adjust a value of the current reference output.
摘要翻译：公开了一种数字可调低电压CMOS电流参考。提供了一种可调谐电流参考电路，其包括耦合到电源电压的电流源电路。电流源电路提供稳定的电流参考输出，而不管电源电压的波动。多个数字可选输入包括在当前参考电路中并耦合到电流源电路。这些输入用于调整当前参考输出的值。

4. 发明申请

US20060181320A1 Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line 审中-公开
标题翻译：用于优化通过传输线传输的接收时钟的占空比的电路
公开(公告)号：US20060181320A1
公开(公告)日：2006-08-17
申请号：US11055851
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03L7/06
CPC分类号： H04L7/033 , H03L7/0814 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L25/0272
摘要： Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.
摘要翻译：数据信号通过传输线组传送到接收IC中的接收器。每组数据信号具有用于同步和检测数据信号的差分时钟。数据信号眼窗随数据信号相对于时钟边缘的定时抖动和使用占空比调整电路从差分时钟检测到的补偿时钟信号的不对称性而变化。错误检测确定时钟不对称是否影响数据信号的眼睛窗口。控制信号选择性地调节产生补偿时钟的差分级的增益，以修改补偿时钟的占空比。数据信号的眼窗被监视并用作伺服控制信号的反馈，以优化用于采样数据信号的经补偿的时钟信号的占空比。

5. 发明申请

US20060181303A1 Data receiver with a programmable reference voltage to optimize timing jitter 失效
标题翻译：具有可编程参考电压的数据接收器，以优化定时抖动
公开(公告)号：US20060181303A1
公开(公告)日：2006-08-17
申请号：US11055805
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03K19/003
CPC分类号： H04L25/0292 , G06F13/4072 , H04L7/0033 , H04L25/0272
摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.
摘要翻译：伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。参考电压可以使用粗调以及精细的数字控制电压增量进行调节。测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。将参考电压的操作值设定为检测定时抖动确定为最小的值。

6. 发明申请

US20080074998A1 SELF-HEALING CHIP-TO-CHIP INTERFACE 有权
标题翻译：自我加工芯片到芯片接口
公开(公告)号：US20080074998A1
公开(公告)日：2008-03-27
申请号：US11948620
申请日：2007-11-30
申请人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
发明人： WIREN BECKER , Daniel Dreps , Frank Ferraiolo , Anand Haridass , Robert Reese
IPC分类号： G01R31/08 , G06F11/00
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

7. 发明申请

US20070288679A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE AND A PERFORMANCE-OPTIMIZED PIN ASSIGNMENT 失效
标题翻译： 276引脚缓存的存储器模块，具有增强的容错能力和性能优化的引脚分配
公开(公告)号：US20070288679A1
公开(公告)日：2007-12-13
申请号：US11695679
申请日：2007-04-03
申请人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Roger Rippens
发明人： Daniel Dreps , Frank Ferraiolo , Kevin Gower , Roger Rippens
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在系统针对高频操作进行了优化。

8. 发明申请

US20060181348A1 Peaking transmission line receiver for logic signals 失效
标题翻译：峰值传输线接收机用于逻辑信号
公开(公告)号：US20060181348A1
公开(公告)日：2006-08-17
申请号：US11055806
申请日：2005-02-11
申请人： Daniel Dreps , Bao Truong , Glen Wiedemeier
发明人： Daniel Dreps , Bao Truong , Glen Wiedemeier
IPC分类号： H03F3/45
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1084
摘要： A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.
摘要翻译：接收器电路被配置为频率补偿差分放大器，其具有耦合到传输线的输出的一个输入以接收传输的信号，而第二输入耦合到参考电压。差分放大器具有等于发射信号的未补偿差分级的增益的高频增益。补偿的差分放大器对于低于高频的信号频率具有衰减的低频增益，对于低频和高频之间的频率具有过渡增益。补偿级为信号的一部分提供补偿响应，并且未补偿级提供未被补偿的放大信号的部分。偏置控制信号确定来自补偿和无补偿级的输出信号的大小是用于定制来自具有不同损耗的传输线的响应的手段。

9. 发明申请

US20080098149A1 SIGNAL HISTORY CONTROLLED SLEW-RATE TRANSMISSION METHOD AND BUS INTERFACE TRANSMITTER 失效
标题翻译：信号历史控制的单向传输方法和总线接口发射机
公开(公告)号：US20080098149A1
公开(公告)日：2008-04-24
申请号：US11962093
申请日：2007-12-21
申请人： Daniel De Araujo , Daniel Dreps , Bhyrav Mutnury
发明人： Daniel De Araujo , Daniel Dreps , Bhyrav Mutnury
IPC分类号： G06F13/00 , H03K5/12
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译：信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。

10. 发明申请

US20060181324A1 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US20060181324A1
公开(公告)日：2006-08-17
申请号：US11215416
申请日：2005-08-30
申请人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
发明人： Daniel Dreps , Frank Ferraiolo , Daniel Friedman , Seongwon Kim , Hector Saenz , Michael Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式