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1. 发明申请

US20060181348A1 Peaking transmission line receiver for logic signals 失效
标题翻译：峰值传输线接收机用于逻辑信号
公开(公告)号：US20060181348A1
公开(公告)日：2006-08-17
申请号：US11055806
申请日：2005-02-11
申请人： Daniel Dreps , Bao Truong , Glen Wiedemeier
发明人： Daniel Dreps , Bao Truong , Glen Wiedemeier
IPC分类号： H03F3/45
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1084
摘要： A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.
摘要翻译：接收器电路被配置为频率补偿差分放大器，其具有耦合到传输线的输出的一个输入以接收传输的信号，而第二输入耦合到参考电压。差分放大器具有等于发射信号的未补偿差分级的增益的高频增益。补偿的差分放大器对于低于高频的信号频率具有衰减的低频增益，对于低频和高频之间的频率具有过渡增益。补偿级为信号的一部分提供补偿响应，并且未补偿级提供未被补偿的放大信号的部分。偏置控制信号确定来自补偿和无补偿级的输出信号的大小是用于定制来自具有不同损耗的传输线的响应的手段。

2. 发明申请

US20090206952A1 DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS 有权
标题翻译：使用高频微调节器进行延时线路调节
公开(公告)号：US20090206952A1
公开(公告)日：2009-08-20
申请号：US12030946
申请日：2008-02-14
申请人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
发明人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
IPC分类号： H03H7/00
CPC分类号： H03H11/265
摘要： A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.
摘要翻译：稳定的延迟线装置包括耦合到节点的主调节器和耦合到节点的多个延迟分支，以通过主调节器接收到节点的电压输出。多个延迟分支中的每一个包括微调节器和延迟线。延迟线耦合到微调节器，使得在每个延迟分支处通过相应的微调节器局部去除未滤波的噪声。

3. 发明申请

US20060181320A1 Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line 审中-公开
标题翻译：用于优化通过传输线传输的接收时钟的占空比的电路
公开(公告)号：US20060181320A1
公开(公告)日：2006-08-17
申请号：US11055851
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03L7/06
CPC分类号： H04L7/033 , H03L7/0814 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L25/0272
摘要： Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.
摘要翻译：数据信号通过传输线组传送到接收IC中的接收器。每组数据信号具有用于同步和检测数据信号的差分时钟。数据信号眼窗随数据信号相对于时钟边缘的定时抖动和使用占空比调整电路从差分时钟检测到的补偿时钟信号的不对称性而变化。错误检测确定时钟不对称是否影响数据信号的眼睛窗口。控制信号选择性地调节产生补偿时钟的差分级的增益，以修改补偿时钟的占空比。数据信号的眼窗被监视并用作伺服控制信号的反馈，以优化用于采样数据信号的经补偿的时钟信号的占空比。

4. 发明申请

US20060181303A1 Data receiver with a programmable reference voltage to optimize timing jitter 失效
标题翻译：具有可编程参考电压的数据接收器，以优化定时抖动
公开(公告)号：US20060181303A1
公开(公告)日：2006-08-17
申请号：US11055805
申请日：2005-02-11
申请人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
发明人： Daniel Dreps , Frank Ferraiolo , Robert Reese , Glen Wiedemeier
IPC分类号： H03K19/003
CPC分类号： H04L25/0292 , G06F13/4072 , H04L7/0033 , H04L25/0272
摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.
摘要翻译：伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。参考电压可以使用粗调以及精细的数字控制电压增量进行调节。测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。将参考电压的操作值设定为检测定时抖动确定为最小的值。

5. 发明授权

US07859318B2 Delay line regulation using high-frequency micro-regulators 有权
标题翻译：使用高频微调节器延迟线调节
公开(公告)号：US07859318B2
公开(公告)日：2010-12-28
申请号：US12030946
申请日：2008-02-14
申请人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
发明人： Daniel Dreps , Daniel Friedman , Seongwon Kim , Hector Saenz , Glen Wiedemeier
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.
摘要翻译：稳定的延迟线装置包括耦合到节点的主调节器和耦合到节点的多个延迟分支，以通过主调节器接收到节点的电压输出。多个延迟分支中的每一个包括微调节器和延迟线。延迟线耦合到微调节器，使得在每个延迟分支处通过相应的微调节器局部去除未滤波的噪声。

6. 发明申请

US20060181304A1 Logic line driver system for providing an optimal driver characteristic 失效
标题翻译：逻辑线驱动系统，提供最佳驱动特性
公开(公告)号：US20060181304A1
公开(公告)日：2006-08-17
申请号：US11055834
申请日：2005-02-11
申请人： Daniel Dreps , John Schiff , Glen Wiedemeier , Joel Ziegelbein
发明人： Daniel Dreps , John Schiff , Glen Wiedemeier , Joel Ziegelbein
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.
摘要翻译：用于片外通信的线路驱动器包括多个并行级，每个并行级具有单独的输入。当将线路驱动器输出节点驱动到逻辑0或逻辑1时，并联级各自具有受控阻抗。线路驱动器控制器用于基于输出节点是在逻辑状态之间转换还是保持静态来选择驱动器级的组合来驱动输出节点。在上电期间，测试程序尝试针对特定符号模式的驱动器级的不同组合，并确定动态和静态情况下线驱动器电阻之间的最佳比例是多少，并存储最佳组合。馈送线路驱动器的数据流被实时采样以确定转换状态，并为每种情况选择最佳数量的驱动级。

7. 发明申请

US20060181302A1 Slew rate control for driver circuit 有权
公开(公告)号：US20060181302A1
公开(公告)日：2006-08-17
申请号：US11055852
申请日：2005-02-11
申请人： Daniel Dreps , John Schief , Glen Wiedemeier , Joel Ziegelbein
发明人： Daniel Dreps , John Schief , Glen Wiedemeier , Joel Ziegelbein
IPC分类号： H03K17/16
CPC分类号： H03K17/164
摘要： The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while slower slew rates may be implemented in the communication channels when crosstalk is more of a concern.

8. 发明申请

US20060076995A1 Adjustable switchpoint receiver 有权
标题翻译：可调开关接收器
公开(公告)号：US20060076995A1
公开(公告)日：2006-04-13
申请号：US10960568
申请日：2004-10-07
申请人： Daniel Dreps , John Schiff , Glen Wiedemeier
发明人： Daniel Dreps , John Schiff , Glen Wiedemeier
IPC分类号： H03K3/037
CPC分类号： H04L25/0292 , H03K5/086 , H03K19/0027
摘要： A signal detector circuit and digital signal receiver implementing the same. In one embodiment the digital signal receiver includes a switch point detector having a detector output and including a transistor array comprising one or more pull-up branches and one or more pull-down branches. A switch point control circuit is coupled to the switch point detector. The switch point control circuit generates branch enable signals for selectively enabling or disabling said one or more pull-up branches and said one or more pull-down branches in a detector output polarity dependent manner.
摘要翻译：信号检测器电路和数字信号接收机实现相同。在一个实施例中，数字信号接收机包括具有检测器输出并具有包括一个或多个上拉分支和一个或多个下拉分支的晶体管阵列的开关点检测器。开关点控制电路耦合到开关点检测器。切换点控制电路产生分支使能信号，用于以检测器输出极性依赖的方式选择性地启用或禁用所述一个或多个上拉分支和所述一个或多个下拉分支。

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