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1. 发明申请

US20090290426A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20090290426A1
公开(公告)日：2009-11-26
申请号：US12123765
申请日：2008-05-20
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

2. 发明授权

US07535787B2 Methods and apparatuses for refreshing non-volatile memory 有权
标题翻译：用于刷新非易失性存储器的方法和装置
公开(公告)号：US07535787B2
公开(公告)日：2009-05-19
申请号：US11810550
申请日：2007-06-06
申请人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
发明人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C11/406 , G11C16/0483 , G11C2211/4062
摘要： Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.
摘要翻译：公开了由于诸如电荷损失的存储器单元费用的变化而刷新非易失性存储器的方法和装置。实施例通常包括电压发生器以产生用于块中的存储器单元的存储器状态的次阈值电压。一旦子阈值电压被施加到字线，状态读取器就确定耦合到字线的存储器单元的状态。如果状态读取器确定耦合到字线的一个或多个存储器单元处于存储器状态，尽管存在子阈值电压，存储器刷新器可以对块中的多个存储单元进行编程。方法实施例通常包括将子阈值电压施加到多个存储器单元的字线，检测多个存储单元中的至少一个存储单元违反状态参数，以及刷新与多个单元相关联的存储单元块。

3. 发明申请

US20080080103A1 MULTIPLE OUTPUT VOLTAGE REGULATOR 失效
标题翻译：多路输出稳压器
公开(公告)号：US20080080103A1
公开(公告)日：2008-04-03
申请号：US11537046
申请日：2006-09-29
申请人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
发明人： Fabrice Paillet , Nick Triantafillou , Azam Barkatullah , Daniel Elmhurst , Peter Harrington , Raymond W. Zeng
IPC分类号： H02H7/00
CPC分类号： H02M3/158 , H02M2001/008 , Y10T307/25
摘要： Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.
摘要翻译：一些实施例包括具有与输出电路相互作用以将源电压转换成至少一个输出电压的输出控制电路的管芯。芯片还可以具有转换器电路，以将输出电压转换成至少一个额外的输出电压。

4. 发明申请

US20060193172A1 High bandwidth datapath load and test of multi-level memory cells 失效
标题翻译：高带宽数据路径负载和多级存储单元的测试
公开(公告)号：US20060193172A1
公开(公告)日：2006-08-31
申请号：US11391509
申请日：2006-03-28
申请人： Daniel Elmhurst , Karthikeyan Ramamurthi , Quan Ngo , Robert Melcher
发明人： Daniel Elmhurst , Karthikeyan Ramamurthi , Quan Ngo , Robert Melcher
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/50004 , G11C29/52 , G11C2029/5002 , G11C2211/5641
摘要： An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.
摘要翻译：一种用于使用高带宽数据路径架构在存储器存储设备中测试多级单元（MLC）的装置和技术。该技术包括用于从多级单元存储器获得第一数据和第二数据的硬件。第一数据与第二数据不同。比较第一数据和第二数据，并且至少部分地基于该比较，对多电平单元存储器进行编程。编程多电平单元存储器包括访问多电平单元存储器中的存储单元，并确定需要编程的第一数据的每个存储单元的位数。

5. 发明授权

US08085591B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US08085591B2
公开(公告)日：2011-12-27
申请号：US12123765
申请日：2008-05-20
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/34 , G11C16/28 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

6. 发明申请

US20080304327A1 Methods and apparatuses for refreshing non-volatile memory 有权
标题翻译：用于刷新非易失性存储器的方法和装置
公开(公告)号：US20080304327A1
公开(公告)日：2008-12-11
申请号：US11810550
申请日：2007-06-06
申请人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
发明人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
IPC分类号： G11C11/401 , G11C16/16 , G11C29/04
CPC分类号： G11C16/3418 , G11C11/406 , G11C16/0483 , G11C2211/4062
摘要： Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.
摘要翻译：公开了由于诸如电荷损失的存储器单元费用的变化而刷新非易失性存储器的方法和装置。实施例通常包括电压发生器以产生用于块中的存储器单元的存储器状态的次阈值电压。一旦子阈值电压被施加到字线，状态读取器就确定耦合到字线的存储器单元的状态。如果状态读取器确定耦合到字线的一个或多个存储器单元处于存储器状态，尽管存在子阈值电压，存储器刷新器可以对块中的多个存储单元进行编程。方法实施例通常包括将子阈值电压施加到多个存储器单元的字线，检测多个存储单元中的至少一个存储单元违反状态参数，以及刷新与多个单元相关联的存储单元块。

7. 发明申请

US20080159005A1 SELECTIVE BIT LINE PRECHARGING IN NON VOLATILE MEMORY 有权
标题翻译：非挥发性存储器中的选择位线预置
公开(公告)号：US20080159005A1
公开(公告)日：2008-07-03
申请号：US11618637
申请日：2006-12-29
申请人： June Lee , Daniel Elmhurst
发明人： June Lee , Daniel Elmhurst
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.
摘要翻译：描述了诸如NAND闪存的闪速存储器件，其具有具有连接到相应位线的存储器单元串的浮动晶体管存储器单元的阵列。描述了选择性预充电位线的结构和方法。

8. 发明申请

US20140293697A1 CHARGE LOSS COMPENSATION METHODS AND APPARATUS 有权
标题翻译：充电损失补偿方法和装置
公开(公告)号：US20140293697A1
公开(公告)日：2014-10-02
申请号：US14290315
申请日：2014-05-29
申请人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
发明人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/34 , G11C16/10 , G11C16/349
摘要： Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.
摘要翻译：用于补偿存储器中的电荷损失的方法和装置包括跟踪主存储器阵列的特定块并通过比较跟踪块的预循环和后循环平均阈值电压来确定电荷损失补偿; 或跟踪主存储器的每个块，并逐个逐块地确定电荷损耗和补偿。

9. 发明授权

US08264882B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/34 , G11C16/28 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

10. 发明申请

US20110199826A1 CHARGE LOSS COMPENSATION METHODS AND APPARATUS 有权
标题翻译：充电损失补偿方法和装置
公开(公告)号：US20110199826A1
公开(公告)日：2011-08-18
申请号：US13093411
申请日：2011-04-25
申请人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
发明人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/34 , G11C16/10 , G11C16/349
摘要： Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.
摘要翻译：用于补偿存储器中的电荷损失的方法和装置包括跟踪主存储器阵列的特定块并通过比较跟踪块的预循环和后循环平均阈值电压来确定电荷损失补偿; 或跟踪主存储器的每个块，并逐个逐块地确定电荷损耗和补偿。

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