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1. 发明申请

US20090290426A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20090290426A1
公开(公告)日：2009-11-26
申请号：US12123765
申请日：2008-05-20
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

2. 发明授权

US08085591B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US08085591B2
公开(公告)日：2011-12-27
申请号：US12123765
申请日：2008-05-20
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/34 , G11C16/28 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

3. 发明申请

US20120075932A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20120075932A1
公开(公告)日：2012-03-29
申请号：US13313379
申请日：2011-12-07
申请人： Violante MOSCHIANO , Daniel Elmhurst , Giovanni Santin
发明人： Violante MOSCHIANO , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

4. 发明申请

US20100097856A1 FLASH MEMORY AND ASSOCIATED METHODS 有权
标题翻译：闪存和相关方法
公开(公告)号：US20100097856A1
公开(公告)日：2010-04-22
申请号：US12643610
申请日：2009-12-21
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/04 , G11C7/06
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译：在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。

5. 发明授权

US08264882B2 Charge loss compensation during programming of a memory device 有权
标题翻译：存储器件编程期间的充电损耗补偿
公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/34 , G11C16/28 , G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

6. 发明授权

US08391061B2 Flash memory and associated methods 有权
标题翻译：闪存和相关方法
公开(公告)号：US08391061B2
公开(公告)日：2013-03-05
申请号：US12643610
申请日：2009-12-21
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译：在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。

7. 发明申请

US20080158986A1 FLASH MEMORY AND ASSOCIATED METHODS 审中-公开
标题翻译：闪存和相关方法
公开(公告)号：US20080158986A1
公开(公告)日：2008-07-03
申请号：US11618652
申请日：2006-12-29
申请人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
发明人： Daniel Elmhurst , Giovanni Santin , Michele Incarnati , Violante Moschiano , Ercole Diiorio
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation, a latch in a cache memory of a NAND flash memory is switched off, and the latch is initialized while the latch is switched off. A read voltage is coupled to a gate of a selected flash memory cell in the NAND flash memory where the selected flash memory cell is coupled to a bit-line, and the bit-line is coupled to an input of the latch while a voltage on the bit-line is changing.
摘要翻译：在一种操作方法中，闪存单元被编程，字线电压耦合到闪存单元，并且间隔地感测闪存单元的状态以产生数据以指示闪存单元的状态。在一种操作方法中，NAND闪存的高速缓冲存储器中的锁存器被关闭，并且在锁存器被关闭时初始化锁存器。读取电压耦合到NAND闪速存储器中所选择的快闪存储器单元的栅极，其中所选闪存单元耦合到位线，并且位线耦合到锁存器的输入，同时电压开位线正在改变。

8. 发明授权

US07535787B2 Methods and apparatuses for refreshing non-volatile memory 有权
标题翻译：用于刷新非易失性存储器的方法和装置
公开(公告)号：US07535787B2
公开(公告)日：2009-05-19
申请号：US11810550
申请日：2007-06-06
申请人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
发明人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C11/406 , G11C16/0483 , G11C2211/4062
摘要： Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.
摘要翻译：公开了由于诸如电荷损失的存储器单元费用的变化而刷新非易失性存储器的方法和装置。实施例通常包括电压发生器以产生用于块中的存储器单元的存储器状态的次阈值电压。一旦子阈值电压被施加到字线，状态读取器就确定耦合到字线的存储器单元的状态。如果状态读取器确定耦合到字线的一个或多个存储器单元处于存储器状态，尽管存在子阈值电压，存储器刷新器可以对块中的多个存储单元进行编程。方法实施例通常包括将子阈值电压施加到多个存储器单元的字线，检测多个存储单元中的至少一个存储单元违反状态参数，以及刷新与多个单元相关联的存储单元块。

9. 发明申请

US20080304327A1 Methods and apparatuses for refreshing non-volatile memory 有权
标题翻译：用于刷新非易失性存储器的方法和装置
公开(公告)号：US20080304327A1
公开(公告)日：2008-12-11
申请号：US11810550
申请日：2007-06-06
申请人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
发明人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
IPC分类号： G11C11/401 , G11C16/16 , G11C29/04
CPC分类号： G11C16/3418 , G11C11/406 , G11C16/0483 , G11C2211/4062
摘要： Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.
摘要翻译：公开了由于诸如电荷损失的存储器单元费用的变化而刷新非易失性存储器的方法和装置。实施例通常包括电压发生器以产生用于块中的存储器单元的存储器状态的次阈值电压。一旦子阈值电压被施加到字线，状态读取器就确定耦合到字线的存储器单元的状态。如果状态读取器确定耦合到字线的一个或多个存储器单元处于存储器状态，尽管存在子阈值电压，存储器刷新器可以对块中的多个存储单元进行编程。方法实施例通常包括将子阈值电压施加到多个存储器单元的字线，检测多个存储单元中的至少一个存储单元违反状态参数，以及刷新与多个单元相关联的存储单元块。

10. 发明授权

US08767476B2 Charge loss compensation methods and apparatus 有权
标题翻译：充电损失补偿方法和装置
公开(公告)号：US08767476B2
公开(公告)日：2014-07-01
申请号：US13093411
申请日：2011-04-25
申请人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
发明人： Violante Moschiano , Daniel Elmhurst , Paul Ruby
IPC分类号： G11C11/34
CPC分类号： G11C16/34 , G11C16/10 , G11C16/349
摘要： Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.
摘要翻译：用于补偿存储器中的电荷损失的方法和装置包括跟踪主存储器阵列的特定块并通过比较跟踪块的预循环和后循环平均阈值电压来确定电荷损失补偿; 或跟踪主存储器的每个块，并逐个逐块地确定电荷损耗和补偿。

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