专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07061860B1 Network traffic shaping 有权
标题翻译：网络流量整形
公开(公告)号：US07061860B1
公开(公告)日：2006-06-13
申请号：US09706969
申请日：2000-11-06
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： A method for shaping network traffic in a computer network is described for packet data networks. The method includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：针对分组数据网络描述了一种用于整形计算机网络中的网络流量的方法。该方法包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

2. 发明授权

US06876659B2 Enqueuing apparatus for asynchronous transfer mode (ATM) virtual circuit merging 失效
标题翻译：异步传输模式（ATM）虚拟电路合并的启动装置
公开(公告)号：US06876659B2
公开(公告)日：2005-04-05
申请号：US09753920
申请日：2001-01-03
申请人： Ange Aznar , Jose Iruella , Daniel Orsatti , Bruno Rene Rousseau
发明人： Ange Aznar , Jose Iruella , Daniel Orsatti , Bruno Rene Rousseau
IPC分类号： H04L12/70 , H04L12/935 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/3081 , H04L2012/5658 , H04L2012/5681 , H04Q11/0478
摘要： A system and method for merging multiple connections that share a same class of service into a single virtual circuit (VC) in an Asynchronous Transfer Mode (ATM) network. A queuing apparatus includes multiple connection queues for each of the connections, and further includes a scheduled queue corresponding to a particular class of service, wherein contents of the connection queues are transferred into the scheduled queue before being transmitted on the VC. A reassembly queue control block (RQCB) defines a chain of buffer control blocks for the connection queues. Each buffer control block corresponds to a cell belonging to a packet of a particular connection and includes a next buffer address and a lock bit. The chain of buffer control blocks is transferred to a scheduled queue control block (SQCB) in response the lock bit indicating a last packet cell.
摘要翻译：一种用于将共享相同类别服务的多个连接合并到异步传输模式（ATM）网络中的单个虚拟电路（VC）中的系统和方法。排队设备包括用于每个连接的多个连接队列，并且还包括对应于特定服务等级的调度队列，其中连接队列的内容在被传送到VC之前被传送到调度队列中。重组队列控制块（RQCB）为连接队列定义了一连串的缓冲区控制块。每个缓冲器控制块对应于属于特定连接的分组的小区，并且包括下一缓冲器地址和锁定位。响应于指示最后一个分组小区的锁定位，缓冲器控制块链被传送到调度队列控制块（SQCB）。

3. 发明授权

US06772371B1 On-line debugging system in a switching node of a data transmission network 失效
标题翻译：数据传输网络交换节点中的在线调试系统
公开(公告)号：US06772371B1
公开(公告)日：2004-08-03
申请号：US09691511
申请日：2000-10-18
申请人： Daniel Orsatti , Dominique Rigal , Bruno Rousseau , Jean-Claude Zunino
发明人： Daniel Orsatti , Dominique Rigal , Bruno Rousseau , Jean-Claude Zunino
IPC分类号： G06F1100
CPC分类号： G06F11/362
摘要： A system and method for freezing a processing unit to facilitate on-line debugging of a protocol engine within a switching node of a data transmission network. In accordance with the system of the present invention, the protocol engine includes a plurality of processing units such as an identification unit, a lookup unit, a traffic management and congestion unit, an enqueue unit, a dequeue unit, a traffic management scheduling unit, a frame transmission unit, a control unit, and a control block unit. The control block unit includes a freeze register containing multiple freeze bits, wherein each freeze bit is associated with one processing unit. In response to setting a freeze bit, resources and settings of a processing unit associated with the set freeze bit are prevented from being changed by the processing unit.
摘要翻译：一种用于冻结处理单元以促进数据传输网络的交换节点内的协议引擎的在线调试的系统和方法。根据本发明的系统，协议引擎包括多个处理单元，例如识别单元，查找单元，业务管理和拥塞单元，入队单元，出队单元，业务管理调度单元，帧发送单元，控制单元和控制块单元。控制块单元包括一个包含多个冻结位的冻结寄存器，其中每个冻结位与一个处理单元相关联。响应于设置冻结位，防止与设置的冻结位相关联的处理单元的资源和设置被处理单元改变。

4. 发明授权

US06680951B1 System and method for selecting multi-rate ports in a data transmission network 失效
标题翻译：在数据传输网络中选择多速率端口的系统和方法
公开(公告)号：US06680951B1
公开(公告)日：2004-01-20
申请号：US09691390
申请日：2000-10-18
申请人： Ange Aznar , Jose Iruela , Daniel Orsatti , Dominique Rigal
发明人： Ange Aznar , Jose Iruela , Daniel Orsatti , Dominique Rigal
IPC分类号： H04L1266
CPC分类号： H04L12/5601 , H04L49/309 , H04L2012/5629 , H04L2012/5681
摘要： A system and method for selecting one port among multiple output ports having various transmission rates attached to an output adapter of a switching node in a data transmission network and enabling it to transmit its data over the network. The system of the present invention includes a storage device that contains a list of identification codes for the ports. The identification code list is arranged in a prioritized order from the port having the highest transmission rate to the port having the lowest transmission rate. The system further includes port service request means that generate a service request signal for each port, wherein the service request signal has a frequency corresponding to the transmission rate of the object port. Port selection means are utilized to, in response to said identification codes and said service request signal, select a requesting port having a highest priority according to its identification code and enabling the selected port to transmit data over the date transmission network.
摘要翻译：一种用于在具有各种传输速率的多个输出端口中选择一个端口的系统和方法，所述传输速率附加到数据传输网络中的交换节点的输出适配器，并使其能够通过网络传输其数据。本发明的系统包括存储装置，该存储装置包含端口的识别码列表。识别码列表以具有最高传输速率的端口以具有最低传输速率的端口的优先顺序排列。该系统还包括为每个端口生成服务请求信号的端口服务请求装置，其中服务请求信号具有对应于对象端口的传输速率的频率。端口选择装置用于响应于所述识别码和所述服务请求信号，根据其识别码选择具有最高优先级的请求端口，并使所选择的端口能够在日期传输网络上传输数据。

5. 发明授权

US09112546B2 Process for performing near field communication (NFC) in an integrated circuit or package also including a FM receiver 有权
标题翻译：在还包括FM接收器的集成电路或封装中执行近场通信（NFC）的过程
公开(公告)号：US09112546B2
公开(公告)日：2015-08-18
申请号：US13516726
申请日：2010-12-21
申请人： Daniel Orsatti , Onno Marcel Kuijken , Pablo Ignacio Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
发明人： Daniel Orsatti , Onno Marcel Kuijken , Pablo Ignacio Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
IPC分类号： H04B5/00 , H04B5/02 , H04B15/06 , H04B7/08
CPC分类号： H04B5/02 , H04B15/06
摘要： A process for performing Near Field Communication (NFC) between a first NFC device and a second NFC device is provided. The first NFC device includes an NFC transceiver and an FM receiver which are both integrated into the same chip. The provided process involves initializing the first NFC device to perform a device detection polling loop for detecting a second NFC device. The device detection polling loop has activity detection periods, which occur periodically. The first NFC transceiver may then perform a slicing procedure, which slices the activity detection periods into small time slots. Each time slot has a duration smaller than a predetermined value so as to reduce the noise generated by harmonics of the NFC operation frequency which might be audible to the user.
摘要翻译：提供了用于在第一NFC设备和第二NFC设备之间执行近场通信（NFC）的过程。第一个NFC设备包括集成在同一芯片中的NFC收发器和FM接收器。所提供的过程涉及初始化第一NFC设备以执行用于检测第二NFC设备的设备检测轮询环路。设备检测轮询循环具有周期性发生的活动检测周期。然后，第一NFC收发器可以执行切片过程，其将活动检测周期切片成小时隙。每个时隙具有小于预定值的持续时间，以便减少由用户可听见的NFC操作频率的谐波产生的噪声。

6. 发明授权

US06754182B1 Method and apparatus for policing cell-based traffic 失效
标题翻译：用于监管基于单元的流量的方法和装置
公开(公告)号：US06754182B1
公开(公告)日：2004-06-22
申请号：US09691508
申请日：2000-10-18
申请人： Ange Aznar , Daniel Orsatti , Jose Iruela , Bruno Rousseau
发明人： Ange Aznar , Daniel Orsatti , Jose Iruela , Bruno Rousseau
IPC分类号： H04L1226
CPC分类号： H04L12/5601 , H04L2012/5636
摘要： A method and system for enforcing a transmission control parameter for a virtual connection comprising multiple cells within an input port. The virtual connection has a nominal inter-cell arrival rate increment. Each of the cells are associated with a theoretical arrival time and an early arrival limit, wherein a difference of the early arrival limit from said theoretical arrival time delineates a lower boundary of a good zone, while the theoretical arrival time minus the sum of the early arrival limit and the nominal inter-cell arrival rate increment delineates an upper boundary of the good zone. The method includes determining an actual arrival time for an incoming cell from the cells that make up the virtual connection. Next, the actual arrival time is compared to the upper boundary and the lower boundary to determine whether or not the actual arrival time falls within the good zone. In response to determining that the actual arrival time falls within the good zone, the incoming cell is identified as conforming to the transmission control parameter. The method and system of the invention allow to use a finite counter for measuring elapsed time at entry ports of ATM switching nodes, a mandatory feature in order to enforce policing, while avoiding having to manage the overflows of the counter.
摘要翻译：一种用于对包括输入端口内的多个单元的虚拟连接实施传输控制参数的方法和系统。虚拟连接具有标称的小区间到达速率增量。每个小区与理论到达时间和早期到达极限相关联，其中早期到达极限与理论到达时间的差异描绘了良好区域的下边界，而理论到达时间减去早期到达限制和标称单元间到达率增量描绘了良好区域的上边界。该方法包括从构成虚拟连接的小区确定进入小区的实际到达时间。接下来，将实际到达时间与上边界和下边界进行比较，以确定实际到达时间是否落在良好区域内。响应于确定实际到达时间落在良好区域内，进入小区被识别为符合传输控制参数。本发明的方法和系统允许使用有限计数器来测量ATM交换节点进入端口的经过时间，这是强制性功能，以便强制执行警务，同时避免必须管理计数器的溢出。

7. 发明授权

US6144637A Data communications 失效
标题翻译：数据通信
公开(公告)号：US6144637A
公开(公告)日：2000-11-07
申请号：US991911
申请日：1997-12-16
申请人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
发明人： Jean Calvignac , Fabrice Verplanken , Daniel Orsatti
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译：描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。每个传入的数据包被引导到适当的队列。多个定时电路中的每一个在一系列频率中以不同的频率工作。选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

8. 发明授权

US5724348A Efficient hardware/software interface for a data switch 失效
标题翻译：高效的数据交换硬件/软件界面
公开(公告)号：US5724348A
公开(公告)日：1998-03-03
申请号：US858156
申请日：1997-05-05
申请人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Mathieu Girard , Daniel Orsatti , Michel Susini , Fabrice Verplanken
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/30 , H04L49/104 , H04L49/254 , H04L49/255 , H04L49/3081 , H04Q11/0478 , H04L2012/5652 , H04L49/3009
摘要： A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.
摘要翻译：使用多端口数据交换元件描述数据交换机，一个或多个输入/输出适配器，用于从交换机外部接收用户数据单元，以及将通过交换单元切换的小区发送到交换机外部的网络，以及控制元件包括一个控制处理器。为了降低数据交换的复杂性，单个控制处理器用于控制处理器所在的控制元件和输入/输出适配器上的硬件模块的操作。控制通过控制单元提供，控制单元通常遍历与用户数据单元相同的数据路径，并且至少在数据交换机内通常符合用户数据单元的格式。控制处理器和硬件模块都能够产生控制单元并将其发送到目标，即控制处理器或硬件模块。

9. 发明授权

US06195335B1 Data switch 失效
标题翻译：数据开关
公开(公告)号：US06195335B1
公开(公告)日：2001-02-27
申请号：US09110917
申请日：1998-07-06
申请人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
发明人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/1576 , H04L2012/5679 , H04L2012/5681
摘要： A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.
摘要翻译：描述包数据交换机，其包括交叉开关结构，其包括用于存储至少一个数据分组的一组交叉点缓冲器，每个数据分组一个用于每个输入/输出对。为每个输入 - 输出对提供输入队列，并且提供装置用于在对应于数据分组的输入 - 输出路由的一个队列中存储输入数据分组。输入调度器在每个输入处重复从多个队列中选择一个队列，并且将数据分组从输入调度器选择的队列从输入队列装置传送到对应于数据分组的输入 - 输出路由的交叉点缓冲区。背压机构被布置为禁止第一选择器对应于相应交叉点缓冲器已满的输入/输出对的队列的选择。最后，输出调度器针对每个输出重复选择对应于输出的交叉点缓冲器之一，并且交换机响应于输出调度器来完成通过存储在由输出调度器选择的交叉点缓冲器中的数据分组的交换结构的传输。

10. 发明授权

US6044079A Statistical packet discard 失效
标题翻译：统计数据包丢弃
公开(公告)号：US6044079A
公开(公告)日：2000-03-28
申请号：US943606
申请日：1997-10-03
申请人： Jean L. Calvignac , Daniel Orsatti , Robert A. Sultan , Fabrice J. Verplanken
发明人： Jean L. Calvignac , Daniel Orsatti , Robert A. Sultan , Fabrice J. Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/5601 , H04L49/309 , H04L2012/5647 , H04L2012/5654
摘要： The present invention is an apparatus that manages Packet-Discard at a switch in an ATM network. The apparatus includes a table having a number of table addresses (or indexes). Each table address stores a record for incoming data cells of a frame. The records indicate whether data cells of the frame are be discarded. The number of possible cell identifiers is greater than the number of table addresses. The apparatus also includes a processor unit which receives a data cell having a cell identifier. The processor unit determines a table key, based on the cell identifier such that the table key is within the range of the table addresses. The processor unit then searches a record in the table associated with the table key to determine whether the data cell is to be discarded.
摘要翻译：本发明是一种在ATM网络中的交换机处理Packet-Discard的装置。该装置包括具有多个表地址（或索引）的表。每个表地址存储帧的传入数据单元的记录。记录表示帧的数据单元是否被丢弃。可能的小区标识符的数量大于表地址的数量。该装置还包括接收具有小区标识符的数据小区的处理器单元。处理器单元基于小区标识符来确定表密钥，使得表密钥在表地址的范围内。处理器单元然后搜索与表键相关联的表中的记录，以确定数据单元是否被丢弃。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式