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1. 发明授权

US09112546B2 Process for performing near field communication (NFC) in an integrated circuit or package also including a FM receiver 有权
标题翻译：在还包括FM接收器的集成电路或封装中执行近场通信（NFC）的过程
公开(公告)号：US09112546B2
公开(公告)日：2015-08-18
申请号：US13516726
申请日：2010-12-21
申请人： Daniel Orsatti , Onno Marcel Kuijken , Pablo Ignacio Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
发明人： Daniel Orsatti , Onno Marcel Kuijken , Pablo Ignacio Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
IPC分类号： H04B5/00 , H04B5/02 , H04B15/06 , H04B7/08
CPC分类号： H04B5/02 , H04B15/06
摘要： A process for performing Near Field Communication (NFC) between a first NFC device and a second NFC device is provided. The first NFC device includes an NFC transceiver and an FM receiver which are both integrated into the same chip. The provided process involves initializing the first NFC device to perform a device detection polling loop for detecting a second NFC device. The device detection polling loop has activity detection periods, which occur periodically. The first NFC transceiver may then perform a slicing procedure, which slices the activity detection periods into small time slots. Each time slot has a duration smaller than a predetermined value so as to reduce the noise generated by harmonics of the NFC operation frequency which might be audible to the user.
摘要翻译：提供了用于在第一NFC设备和第二NFC设备之间执行近场通信（NFC）的过程。第一个NFC设备包括集成在同一芯片中的NFC收发器和FM接收器。所提供的过程涉及初始化第一NFC设备以执行用于检测第二NFC设备的设备检测轮询环路。设备检测轮询循环具有周期性发生的活动检测周期。然后，第一NFC收发器可以执行切片过程，其将活动检测周期切片成小时隙。每个时隙具有小于预定值的持续时间，以便减少由用户可听见的NFC操作频率的谐波产生的噪声。

2. 发明申请

US20130045679A1 PROCESS FOR PERFORMING NEAR FIELD COMMUNICATION (NFC) IN AN INTEGRATED CIRCUIT OR PACKAGE ALSO INCLUDING A FM RECEIVER 有权
标题翻译：在集成电路中进行近场通信（NFC）的过程或包括FM接收器的包
公开(公告)号：US20130045679A1
公开(公告)日：2013-02-21
申请号：US13516726
申请日：2010-12-21
申请人： Daniel Orsatti , Onno Kuijken , Pablo Ignacío Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
发明人： Daniel Orsatti , Onno Kuijken , Pablo Ignacío Gimeno Monge , Steven Terryn , Roland Van Der Tuijn
IPC分类号： H04B5/02 , H04B1/10
CPC分类号： H04B5/02 , H04B15/06
摘要： A process for performing Near Field Communication (NFC) between a first NFC device and a second NFC device is provided. The first NFC device includes an NFC transceiver and an FM receiver which are both integrated into the same chip. The provided process involves initializing the first NFC device to perform a device detection polling loop for detecting a second NFC device. The device detection polling loop has activity detection periods, which occur periodically. The first NFC transceiver may then perform a slicing procedure, which slices the activity detection periods into small time slots. Each time slot has a duration smaller than a predetermined value so as to reduce the noise generated by harmonics of the NFC operation frequency which might be audible to the user.
摘要翻译：提供了用于在第一NFC设备和第二NFC设备之间执行近场通信（NFC）的过程。第一个NFC设备包括集成在同一芯片中的NFC收发器和FM接收器。所提供的过程涉及初始化第一NFC设备以执行用于检测第二NFC设备的设备检测轮询环路。设备检测轮询循环具有周期性发生的活动检测周期。然后，第一NFC收发器可以执行切片过程，其将活动检测周期切片成小时隙。每个时隙具有小于预定值的持续时间，以便减少由用户可听见的NFC操作频率的谐波产生的噪声。

3. 发明授权

US07965728B2 Buffer for driving capacitive load 有权
标题翻译：用于驱动容性负载的缓冲器
公开(公告)号：US07965728B2
公开(公告)日：2011-06-21
申请号：US11599178
申请日：2006-11-14
申请人： Steven Terryn
发明人： Steven Terryn
IPC分类号： H03K3/00
CPC分类号： H03F3/3022 , H03F1/02 , H03F1/0205 , H03F2200/297 , H03F2200/336
摘要： A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.
摘要翻译：缓冲电路缓冲从本地振荡器发生器到混合电路的输入信号，并具有具有两个输入的推挽电路，第一个耦合到第一输入信号，第二个输入耦合到缓冲的输入信号的版本，具有与第一输入信号相关的相位。通过将第二输入耦合到缓冲版本而不是输入信号，呈现给先前电路的负载可以减少一半，同时保持降低的功耗。通过使用与第一输入信号相关的信号作为第二输入，可以保持推挽电路的正常操作。来自LO发生器的输入信号可以是差分IQ信号，并且进一步输入信号的缓冲版本与第一输入信号同相。

4. 发明授权

US08175202B2 Receiver with clock drift compensation 有权
标题翻译：接收器带时钟漂移补偿
公开(公告)号：US08175202B2
公开(公告)日：2012-05-08
申请号：US11503408
申请日：2006-08-11
申请人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
发明人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
IPC分类号： H04B1/10
CPC分类号： H04L27/22 , H04L7/0041 , H04L7/0062 , H04L7/007
摘要： A receiver is described including circuitry for deriving at least a first stream of first digitized samples from a received analog signal at a first sampling rate, circuitry for selecting a first sampling point and at least a second sampling point, a demodulator for demodulating first and second symbols from the at least first stream of samples based on the first and the at least second sampling points, and circuitry for determining a value related to a demodulation accuracy for the first and second symbols and for outputting a signal, the circuitry for selecting being adapted to alter the sampling point based on the signal. By assessing a demodulation accuracy in real time clock drift can be compensated. The demodulation accuracy can be a value related to a phase error or an error energy such as EVM or DEVM for each demodulated symbol.
摘要翻译：描述了接收机，其包括用于以第一采样率从接收到的模拟信号导出至少第一数字化采样的第一流的电路，用于选择第一采样点和至少第二采样点的电路，用于解调第一和第二采样点的解调器基于第一和至少第二采样点的来自至少第一采样流的符号以及用于确定与第一和第二符号的解调精度相关的值并用于输出信号的电路，用于选择的电路被适配根据信号改变采样点。通过评估实时的解调精度，可以补偿时钟漂移。对于每个解调符号，解调精度可以是与相位误差或诸如EVM或DEVM的误差能量相关的值。

5. 发明授权

US08280338B2 Mixer cell with a dynamic bleed circuit 有权
标题翻译：混合器具有动态放电电路
公开(公告)号：US08280338B2
公开(公告)日：2012-10-02
申请号：US12509327
申请日：2009-07-24
申请人： Dieter Joos , Steven Terryn
发明人： Dieter Joos , Steven Terryn
IPC分类号： H04B1/26
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/165 , H03D2200/0025 , H03D2200/0084 , H03D2200/0088
摘要： A mixer is described having a Gilbert cell structure including a first input and a second input for inputting an RF signal, a third input and a fourth input for inputting a local oscillator signal, a first output and a second output for outputting an IF signal, a plurality of switches for converting the RF signal to an IF signal, and a dynamic bleed circuit for dynamically reducing the dc-current of the switches at the switching-point. As the dc-current of the switches is reduced at the point of commutation, the 1/f-noise is also strongly reduced without degrading the linearity. The switching happens at twice the local oscillator frequency. The mixer also includes a common mode feedback circuit that feeds the common mode signal, optionally amplified, to a common mode feedback control device that is in series between the dynamic bleed circuit and the supply voltage.
摘要翻译：描述了具有吉尔伯特单元结构的混频器，其包括用于输入RF信号的第一输入和第二输入，用于输入本地振荡器信号的第三输入和第四输入，用于输出IF信号的第一输出和第二输出，用于将RF信号转换成IF信号的多个开关，以及动态放电电路，用于动态地减小开关点处的开关的直流电流。由于开关点的直流电流在换向点减小，所以1 / f噪声也大大降低，而不降低线性度。切换发生在本机振荡器频率的两倍。混频器还包括共模反馈电路，其将共模信号（可选地放大）馈送到串联在动态放电电路和电源电压之间的共模反馈控制装置。

6. 发明申请

US20080111590A1 Buffer for driving capacitive load 有权
标题翻译：用于驱动容性负载的缓冲器
公开(公告)号：US20080111590A1
公开(公告)日：2008-05-15
申请号：US11599178
申请日：2006-11-14
申请人： Steven Terryn
发明人： Steven Terryn
IPC分类号： H03K3/00
CPC分类号： H03F3/3022 , H03F1/02 , H03F1/0205 , H03F2200/297 , H03F2200/336
摘要： A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.
摘要翻译：缓冲电路缓冲从本地振荡器发生器到混合电路的输入信号，并具有具有两个输入的推挽电路，第一个耦合到第一输入信号，第二个输入耦合到缓冲的输入信号的版本，具有与第一输入信号相关的相位。通过将第二输入耦合到缓冲版本而不是输入信号，呈现给先前电路的负载可以减少一半，同时保持降低的功耗。通过使用与第一输入信号相关的信号作为第二输入，可以保持推挽电路的正常操作。来自LO发生器的输入信号可以是差分IQ信号，并且进一步输入信号的缓冲版本与第一输入信号同相。

7. 发明申请

US20070036247A1 Receiver with frequency offset compensation for M-state phase modulation 有权
标题翻译：具有频率偏移补偿的接收机，用于M态相位调制
公开(公告)号：US20070036247A1
公开(公告)日：2007-02-15
申请号：US11503406
申请日：2006-08-11
申请人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
发明人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
IPC分类号： H04L27/06 , H04B1/10
CPC分类号： H04L27/22 , H04L2027/0065 , H04L2027/0095
摘要： Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples from a received analog signal at a first sampling rate and identify a first frequency offset based on a plurality of parallel correlations using complex reference signals which differ from each other by phase offsets. A second frequency offset is identified based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator. The methods and apparatus may be used in a Bluetooth receiver.
摘要翻译：描述了用于无线接收机的方法和装置，其以第一采样率从接收到的模拟信号中导出至少第一数字化采样的第一流，并且使用复数参考信号来识别基于多个并行相关的第一频率偏移相互偏移。基于从第一数字化样本流解调的每个符号跟踪解调精度来识别第二频率偏移。这些频率偏移可用于旋转解调器中的判定区域。方法和装置可以用在蓝牙接收机中。

8. 发明授权

US08155250B2 Receiver with frequency offset compensation for M-state phase modulation 有权
标题翻译：具有频率偏移补偿的接收机，用于M态相位调制
公开(公告)号：US08155250B2
公开(公告)日：2012-04-10
申请号：US11503406
申请日：2006-08-11
申请人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
发明人： Pietro Capretta , Steven Terryn , Jean-Jacques Schmit
IPC分类号： H04L27/06
CPC分类号： H04L27/22 , H04L2027/0065 , H04L2027/0095
摘要： Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples from a received analog signal at a first sampling rate and identify a first frequency offset based on a plurality of parallel correlations using complex reference signals which differ from each other by phase offsets. A second frequency offset is identified based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator. The methods and apparatus may be used in a Bluetooth receiver.
摘要翻译：描述了用于无线接收机的方法和装置，其以第一采样率从接收到的模拟信号中导出至少第一数字化采样的第一流，并且使用复数参考信号来识别基于多个并行相关的第一频率偏移相互偏移。基于从第一数字化样本流解调的每个符号跟踪解调精度来识别第二频率偏移。这些频率偏移可用于旋转解调器中的判定区域。方法和装置可以用在蓝牙接收机中。

9. 发明授权

US07692484B2 Bandwidth calibration of active filter 有权
标题翻译：有源滤波器的带宽校准
公开(公告)号：US07692484B2
公开(公告)日：2010-04-06
申请号：US11588107
申请日：2006-10-26
申请人： Steven Terryn , Dieter Joos
发明人： Steven Terryn , Dieter Joos
IPC分类号： H03K5/00
CPC分类号： H03F1/08 , H03F3/45475 , H03F2200/264 , H03F2203/45048 , H03F2203/45138 , H03F2203/45526 , H03H11/1291
摘要： An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.
摘要翻译：有源RC滤波器具有运算放大器和偏置电路，其被布置为偏置运算放大器以根据滤波器的期望极点频率设置运算放大器的增益带宽乘积。偏置电路可根据RC校准电路的输出进行操作。运算放大器可以是OTA跨导放大器，并且偏置电路可以被布置成在跨导放大器的输入处保持R和跨导的恒定乘积。该偏置可以有助于更精确地设置极点频率，从而可以减少为提供制造工艺变化而需要提供的带宽余量。

10. 发明申请

US20100029234A1 MIXER CELL WITH A DYNAMIC BLEED CIRCUIT 有权
标题翻译：混合电池与动态放电电路
公开(公告)号：US20100029234A1
公开(公告)日：2010-02-04
申请号：US12509327
申请日：2009-07-24
申请人： Dieter Joos , Steven Terryn
发明人： Dieter Joos , Steven Terryn
IPC分类号： H04B1/16
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/165 , H03D2200/0025 , H03D2200/0084 , H03D2200/0088
摘要： A mixer is described having a Gilbert cell structure including a first input and a second input for inputting an RF signal, a third input and a fourth input for inputting a local oscillator signal, a first output and a second output for outputting an IF signal, a plurality of switches for converting the RF signal to an IF signal, and a dynamic bleed circuit for dynamically reducing the dc-current of the switches at the switching-point. As the dc-current of the switches is reduced at the point of commutation, the 1/f-noise is also strongly reduced without degrading the linearity. The switching happens at twice the local oscillator frequency. The mixer also includes a common mode feedback circuit that feeds the common mode signal, optionally amplified, to a common mode feedback control device that is in series between the dynamic bleed circuit and the supply voltage.
摘要翻译：描述了具有吉尔伯特单元结构的混频器，其包括用于输入RF信号的第一输入和第二输入，用于输入本地振荡器信号的第三输入和第四输入，用于输出IF信号的第一输出和第二输出，用于将RF信号转换成IF信号的多个开关，以及动态放电电路，用于动态地减小开关点处的开关的直流电流。由于开关点的直流电流在换向点减小，所以1 / f噪声也大大降低，而不降低线性度。切换发生在本机振荡器频率的两倍。混频器还包括共模反馈电路，其将共模信号（可选地放大）馈送到串联在动态放电电路和电源电压之间的共模反馈控制装置。

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