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    • 3. 发明授权
    • Method and apparatus for using a bus as a data storage node
    • 一种使用总线作为数据存储节点的方法和装置
    • US06725305B1
    • 2004-04-20
    • US09474412
    • 1999-12-29
    • Hyun LeeDavid W. PotterLai Q. Pham
    • Hyun LeeDavid W. PotterLai Q. Pham
    • G06F1300
    • G06F13/4077
    • The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.
    • 本发明是一种通过利用总线的固有存储容量来在总线上动态地保持有效数据逻辑电平的方法和装置。 通过消除使用有效的总线管理器和空循环来增加总线速度。 相反,使用两相时钟,总线驱动器在时钟的第一阶段将数据驱动到总线上,并且在总线时钟的第二阶段开始时被关断。 接收装置在总线时钟的第二阶段期间锁存数据。 因此,不需要空循环或总线保护电路,但是在连续驱动器之间没有总线争用,也没有浮动节点条件。
    • 5. 发明授权
    • Clock gated bus keeper
    • 时钟门控巴士管家
    • US06484267B1
    • 2002-11-19
    • US09474413
    • 1999-12-29
    • Hyun LeeDavid W. Potter
    • Hyun LeeDavid W. Potter
    • G06F104
    • G06F13/4077
    • The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.
    • 本发明包括时钟总线保持器电路,其在时钟周期的前半部分期间不驱动总线,然后在时钟周期的后半部分的时钟周期的前半部分期间保持被驱动到总线上的值。 因此,总线上的真实数据驱动器在时钟周期的前半部分驱动总线,而不需要克服由总线管理器驱动的值,但是在时钟周期的后半段,总线管理器保持在 时钟周期的前半部分。 以这种方式,真正的总线数据驱动器和总线管理器之间没有总线争用。