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1. 发明授权

US6139696A Method and apparatus for forming a layer on a substrate 失效
公开(公告)号：US6139696A
公开(公告)日：2000-10-31
申请号：US425815
申请日：1999-10-25
申请人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
发明人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
IPC分类号： C23C14/35 , H01J37/32 , H01L21/316 , C23C14/34
CPC分类号： H01J37/321 , C23C14/352 , C23C14/358 , H01L21/02112 , H01L21/02266 , H01L21/31629
摘要： A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

2. 发明授权

US5308788A Temperature controlled process for the epitaxial growth of a film of material 失效
标题翻译：用于材料膜外延生长的温度控制过程
公开(公告)号：US5308788A
公开(公告)日：1994-05-03
申请号：US49645
申请日：1993-04-19
申请人： Jon T. Fitch , Dean J. Denning , Carlos A. Mazure
发明人： Jon T. Fitch , Dean J. Denning , Carlos A. Mazure
IPC分类号： C30B25/10 , C30B25/14 , H01L21/205 , H01L21/00 , H01L21/02 , H01L21/20 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262
摘要： A ramp activated low temperature quality epitaxial growth process. A substrate is pre-conditioned and a passivation layer overlying the substrate surface is formed. The substrate is introduced into a process chamber having a controlled temperature. A process chamber purge technique is used to remove oxygen and contaminants from the process chamber before epitaxial growth begins. A process gas, which has an epitaxial growth species, a process chamber purging species and other possible species, is introduced into the process chamber at a low temperature. The process gas and the passivation layer keep the process chamber environment and the substrate surface free from contamination and free from native oxide growth before and, in some cases, during epitaxial growth. The process chamber temperature is gradually elevated to initiate a quality epitaxial growth by starting growth relative to decomposition of the passivation layer.
摘要翻译：斜坡激活了低温质量外延生长过程。预处理衬底并形成覆盖衬底表面的钝化层。将衬底引入具有受控温度的处理室中。在外延生长开始之前，使用处理室吹扫技术从处理室中除去氧气和污染物。具有外延生长物质的处理气体，处理室清洗物质和其它可能的物质在低温下被引入处理室。工艺气体和钝化层保持处理室环境和衬底表面在外延生长之前和/或在某些情况下在外延生长期间没有污染并且没有自然氧化物生长。通过相对于钝化层的分解开始生长，处理室温度逐渐升高以引发质量外延生长。

3. 发明授权

US08722530B2 Method of making a die with recessed aluminum die pads 有权
标题翻译：用凹槽铝模片制作模具的方法
公开(公告)号：US08722530B2
公开(公告)日：2014-05-13
申请号：US13192976
申请日：2011-07-28
申请人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
发明人： Gregory S. Spencer , Phillip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
IPC分类号： H01L23/48 , H01L33/62 , H01L21/768 , H01L23/488
CPC分类号： H01L21/76879 , H01L21/31053 , H01L21/31056 , H01L21/76804 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/0362 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05681 , H01L2224/05686 , H01L2924/00014 , H01L2924/1305 , H01L2924/1461 , H01L2924/00012 , H01L2924/04941 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
摘要翻译：制造半导体器件的方法包括形成电互连层，在互连层上形成第一介电层，在互连层的第一电互连上在第一介电层中形成开口，在第一电介质上形成铝层蚀刻所述铝层以形成铝管芯焊盘，在所述铝管芯焊盘和所述第一介电层上形成第二电介质层，以及通过所述第一和第二电介质层形成导电通孔以接触所述互连的第二电互连层。

4. 发明授权

US06500315B1 Method and apparatus for forming a layer on a substrate 失效
标题翻译：在基板上形成层的方法和装置
公开(公告)号：US06500315B1
公开(公告)日：2002-12-31
申请号：US09631400
申请日：2000-08-03
申请人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
发明人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
IPC分类号： C23C1600
CPC分类号： H01J37/321 , C23C14/352 , C23C14/358 , H01L21/02112 , H01L21/02266 , H01L21/31629
摘要： A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).
摘要翻译：公开了一种在衬底上形成层的方法和装置。根据一个实施例，将衬底（901）放置在包括线圈（16）和屏蔽（14）的腔室（30）中，其中线圈和屏蔽件通过隔离/支撑构件（32）电隔离，具有与所述线圈的表面基本相邻的第一表面（321），并具有与所述屏蔽件的表面基本相邻的第二表面（322）。然后在衬底（901）上沉积一层（1002,1102）。

5. 发明授权

US06218302B1 Method for forming a semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US06218302B1
公开(公告)日：2001-04-17
申请号：US09121068
申请日：1998-07-21
申请人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
发明人： Gregor Braeckelmann , Ramnath Venkatraman , Matthew Thomas Herrick , Cindy R. Simpson , Robert W. Fiordalice , Dean J. Denning , Ajay Jain , Cristiano Capasso
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76882 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/05546 , H01L2224/05567 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2224/05552 , H01L2924/013 , H01L2924/0105 , H01L2924/01026
摘要： An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.
摘要翻译：互连（60）形成在衬底（10）上。在一个实施例中，将覆盖在衬底（10）上的粘合/阻挡层（81），铜合金晶种层（42）和铜膜（43）沉积，并且将衬底（10）退火。在替代实施例中，在衬底上沉积铜膜，并对铜膜进行退火。在另一个实施例中，在基板（10）上沉积粘合/阻挡层（81），种子层（82），导电膜（83）和铜合金封盖膜（84），以形成互连（92）。沉积和退火步骤可以在公共处理平台上进行。

6. 发明授权

US06187682B1 Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of material 失效
标题翻译：惰性等离子体气体表面清洁过程是用物理气相沉积（PVD）进行的
公开(公告)号：US06187682B1
公开(公告)日：2001-02-13
申请号：US09084276
申请日：1998-05-26
申请人： Dean J. Denning , Rama I. Hegde , Sam S. Garcia , Robert W. Fiordalice
发明人： Dean J. Denning , Rama I. Hegde , Sam S. Garcia , Robert W. Fiordalice
IPC分类号： H01L21311
CPC分类号： H01L21/76843 , C23C14/022 , C23C14/358 , H01L21/02046 , H01L21/28518 , H01L21/2855 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/76804 , H01L21/76807 , H01L21/76814 , Y10S438/913
摘要： A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (26) into a chamber (12). A plasma (30) is generated within the chamber (12) using an inert, noble, or reducing gas. The gas is ionized to form ions (32) within the plasma (30). Power is provided to various components (16, 22, and 24) within the chamber (12) to ensure that the ions (32) are accelerated towards the wafer (26) during first stages of wafer processing. This acceleration of the ions (32) towards the wafer (26) will clean a surface of the wafer (26). Following this cleaning operation, power supplied within the chamber (12) is altered to accelerate the ions (32) into a reverse direction so that the ions (32) impact a sputter target (20). Due to ionic bombardment of the target (20), a material is sputtered onto a clean surface of the wafer (26) in an insitu manner.
摘要翻译：将物理溅射操作连同执行清洁操作的方法开始于将晶片（26）放入室（12）中。使用惰性，贵重或还原气体在室（12）内产生等离子体（30）。气体被离子化以在等离子体（30）内形成离子（32）。功率被提供到腔室（12）内的各种部件（16,22和24），以确保离子（32）在晶片处理的第一阶段期间朝向晶片（26）加速。离子（32）朝向晶片（26）的加速将清洁晶片（26）的表面。在该清洁操作之后，改变在室（12）内供应的功率以将离子（32）加速到相反方向，使得离子（32）撞击溅射靶（20）。由于靶（20）的离子轰击，材料以本体的方式溅射到晶片（26）的清洁表面上。

7. 发明授权

US09209078B2 Method of making a die with recessed aluminum die pads 有权
标题翻译：用凹槽铝模片制作模具的方法
公开(公告)号：US09209078B2
公开(公告)日：2015-12-08
申请号：US14230875
申请日：2014-03-31
申请人： Gregory S. Spencer , Philip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
发明人： Gregory S. Spencer , Philip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
IPC分类号： H01L23/48 , H01L33/62 , H01L21/768 , H01L21/3105 , H01L23/00 , H01L23/488
CPC分类号： H01L21/76879 , H01L21/31053 , H01L21/31056 , H01L21/76804 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/0362 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05681 , H01L2224/05686 , H01L2924/00014 , H01L2924/1305 , H01L2924/1461 , H01L2924/00012 , H01L2924/04941 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
摘要翻译：制造半导体器件的方法包括形成电互连层，在互连层上形成第一介电层，在互连层的第一电互连上在第一介电层中形成开口，在第一电介质上形成铝层蚀刻所述铝层以形成铝管芯焊盘，在所述铝管芯焊盘和所述第一介电层上形成第二电介质层，以及通过所述第一和第二电介质层形成导电通孔以接触所述互连的第二电互连层。

8. 发明申请

US20140213050A1 METHOD OF MAKING A DIE WITH RECESSED ALUMINUM DIE PADS 有权
标题翻译：制造带有凹陷铝箔垫片的方法
公开(公告)号：US20140213050A1
公开(公告)日：2014-07-31
申请号：US14230875
申请日：2014-03-31
申请人： GREGORY S. SPENCER , Philip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
发明人： GREGORY S. SPENCER , Philip E. Crabtree , Dean J. Denning , Kurt H. Junker , Gerald A. Martin
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/31053 , H01L21/31056 , H01L21/76804 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/0362 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05681 , H01L2224/05686 , H01L2924/00014 , H01L2924/1305 , H01L2924/1461 , H01L2924/00012 , H01L2924/04941 , H01L2924/01029 , H01L2924/00 , H01L2224/05552
摘要： A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
摘要翻译：制造半导体器件的方法包括形成电互连层，在互连层上形成第一介电层，在互连层的第一电互连上在第一介电层中形成开口，在第一电介质上形成铝层蚀刻所述铝层以形成铝管芯焊盘，在所述铝管芯焊盘和所述第一介电层上形成第二电介质层，以及通过所述第一和第二电介质层形成导电通孔以接触所述互连的第二电互连层。

9. 发明授权

US06476623B1 Percent backsputtering as a control parameter for metallization 失效
标题翻译：反向溅射的百分比作为金属化的控制参数
公开(公告)号：US06476623B1
公开(公告)日：2002-11-05
申请号：US09666759
申请日：2000-09-21
申请人： Scott C. Bolton , Dean J. Denning , Sam S. Garcia
发明人： Scott C. Bolton , Dean J. Denning , Sam S. Garcia
IPC分类号： G01R2708
CPC分类号： C23C14/345 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76838
摘要： A method for depositing a first metal layer such as tantalum or copper on a patterned semiconductor wafer using a metal sputtering tool that typically includes an electrically biased wafer chuck is disclosed. Initially, a first test wafer is placed on the wafer chuck and a first test layer of materials is deposited on the first test wafer. During the deposition of the first test layer on the first test wafer, the wafer receives the electrical bias at a first level. A second test wafer is then placed on the wafer chuck and a second test layer of material is deposited with the second wafer receiving a second level of electrical bias. The difference in thickness between the first layer and the second layer is then determined. If the difference in thickness is within a predetermined range, the metal sputtering chamber is qualified to deposit a production layer on a production semiconductor wafer.
摘要翻译：公开了一种使用通常包括电偏置晶片卡盘的金属溅射工具在图案化半导体晶片上沉积诸如钽或铜的第一金属层的方法。首先，将第一测试晶片放置在晶片卡盘上，并将第一测试层材料沉积在第一测试晶片上。在将第一测试层沉积在第一测试晶片上时，晶片在第一级接收电偏压。然后将第二测试晶片放置在晶片卡盘上，并且第二测试层材料沉积，第二晶片接收第二级电偏压。然后确定第一层和第二层之间的厚度差。如果厚度差在预定范围内，则金属溅射室有资格在生产半导体晶片上沉积生产层。

10. 发明授权

US06294458B1 Semiconductor device adhesive layer structure and process for forming structure 失效
标题翻译：半导体器件粘合层结构及其结构工艺
公开(公告)号：US06294458B1
公开(公告)日：2001-09-25
申请号：US09494458
申请日：2000-01-31
申请人： Jiming Zhang , Dean J. Denning , Sam S. Garcia , Scott K. Pozder
发明人： Jiming Zhang , Dean J. Denning , Sam S. Garcia , Scott K. Pozder
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76814 , H01L21/76826
摘要： The formation of an adhesion/interlayer region (410) of a semiconductor substrate device (404) before barrier layer (412) deposition provides improved adhesion of the barrier layer (412) to the underlying dielectric (404) and increases strength to the next interconnect layer without altering the function of the barrier layer (412) to limit Cu diffusion into the dielectric substrate (404). The adhesion/interlayer region (410) is formed in an inlaid structure (400, 500) of a semiconductor wafer. The inlaid structure (400, 500) is connected to upper or lower metal layers through vias in the dielectric layer (404) to a copper layer. The adhesion/interlayer region is formed by flowing a treating gas in a glow discharge process of the dielectric substrate in a chamber either attached or separated from the barrier deposition chamber (300). The barrier layer (412) and the adhesion/interlayer region (410) can be formed in this inlaid structure (400, 500) of a semiconductor wafer. The treating gas (212, 320) can be nitrogen, hydrogen, gases containing carbon atoms, or some other suitable gas.
摘要翻译：在阻挡层（412）沉积之前形成半导体衬底器件（404）的粘合/层间区域（410）提供了阻挡层（412）与下面的电介质（404）的改善的粘合性，并且增强了下一个互连的强度而不改变阻挡层（412）的功能以限制扩散到电介质基板（404）中。粘附/层间区域（410）以半导体晶片的镶嵌结构（400,500）形成。镶嵌结构（400,500）通过介电层（404）中的通孔连接到上金属层或下金属层至铜层。通过使电介质基板的辉光放电过程中的处理气体在与阻挡沉积室（300）连接或分离的室中流动来形成粘附/层间区域。可以在半导体晶片的该镶嵌结构（400,500）中形成阻挡层（412）和粘附/层间区域（410）。处理气体（212,320）可以是氮气，氢气，含有碳原子的气体或一些其它合适的气体。

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