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1. 发明授权

US08900403B2 Semiconductor processing system having multiple decoupled plasma sources 有权
标题翻译：具有多个解耦等离子体源的半导体处理系统
公开(公告)号：US08900403B2
公开(公告)日：2014-12-02
申请号：US13104925
申请日：2011-05-10
申请人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Richard Gottscho
发明人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Richard Gottscho
IPC分类号： H01L21/3065 , C23F1/08 , H01J37/32
CPC分类号： H01L21/67069 , H01J37/32082 , H01J37/32633 , H01J37/32899 , H01L21/3065
摘要： A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.
摘要翻译：半导体基板处理系统包括具有处理区域和基板支撑体的室。该系统包括设置在基板支撑件上方的室内的顶板组件。顶板组件包括分别形成在顶板组件的下表面中的第一组和第二组等离子体微室。气体供应通道的第一网络通过顶板组件形成，以将第一工艺气体流动到第一组等离子体微室，以转化为第一等离子体。通过顶板组件形成一组排气通道。第二组等离子体微室形成在排气通道组内。气体供应通道的第二网络通过顶板组件形成，以将第二工艺气体流动到第二组等离子体微室，以转化为第二等离子体。

2. 发明授权

US07279433B2 Deposition and patterning of boron nitride nanotube ILD 有权
标题翻译：氮化硼纳米管的沉积和图案ILD
公开(公告)号：US07279433B2
公开(公告)日：2007-10-09
申请号：US10945319
申请日：2004-09-20
申请人： Peter L. G. Ventzek , Kurt Junker , Marius Orlowski
发明人： Peter L. G. Ventzek , Kurt Junker , Marius Orlowski
IPC分类号： H01L21/31
CPC分类号： H01L21/02112 , B82Y10/00 , H01L21/02282 , H01L21/318 , H01L21/76801 , H01L21/76813 , H01L21/76819 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.
摘要翻译：本文公开了形成电介质层的方法。根据该方法，提供第一材料（303），其包括纳米颗粒在液体介质中的悬浮液。然后通过蒸发过程从悬浮液在基底上形成介电层（305）。

3. 发明授权

US07371677B2 Laterally grown nanotubes and method of formation 有权
标题翻译：侧生长的纳米管和形成方法
公开(公告)号：US07371677B2
公开(公告)日：2008-05-13
申请号：US11240241
申请日：2005-09-30
申请人： Marius K. Orlowski , Shahid Rauf , Peter L. G. Ventzek
发明人： Marius K. Orlowski , Shahid Rauf , Peter L. G. Ventzek
IPC分类号： H01L21/31 , H01L21/44
CPC分类号： H01L21/76838 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/89 , Y10S977/891 , Y10S977/932 , Y10S977/939 , H01L2924/00
摘要： A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.
摘要翻译：半导体器件具有由碳纳米管形成的横向导体或迹线。覆盖衬底上形成牺牲层。覆盖在牺牲层上的电介质层。通过去除位于两列金属催化剂之间的介电层和牺牲层的一部分来形成侧向开口。横向开口包括颈部和空腔部分，其用作用于生长纳米管的约束空间。使用等离子体来施加形成控制纳米管形成方向的电场的电荷。来自每列金属催化剂的纳米管横向生长并邻接或合并成一个纳米管。与纳米管的接触可以由金属催化剂的颈部或者柱子制成。

4. 发明授权

US07592248B2 Method of forming semiconductor device having nanotube structures 失效
标题翻译：形成具有纳米管结构的半导体器件的方法
公开(公告)号：US07592248B2
公开(公告)日：2009-09-22
申请号：US11298148
申请日：2005-12-09
申请人： Peter L. G. Ventzek , Marius K. Orlowski
发明人： Peter L. G. Ventzek , Marius K. Orlowski
IPC分类号： H01L21/4763
CPC分类号： H01L21/32 , B82Y10/00 , B82Y30/00 , H01L21/0331 , H01L21/76801 , H01L21/76802 , H01L2221/1094
摘要： A semiconductor device having upright dielectric nanotubes at an inter-layer dielectric level and method of manufacturing such a device is disclosed. The use of a catalyst is proposed in the disclosed manufacturing flow that facilitates growth of upright dielectric nanotubes having ultra low-k values that form all or part of the dielectric material for an ILD. In one embodiment, carbon nanotubes form interlayer conducting vias. In another embodiment dielectric material nanotubes form reinforcing pillars. The integration of catalysts is proposed to accommodate both upright dielectric and upright conducting nanotube fabrication in the same layer.
摘要翻译：公开了一种具有层间绝缘水平的直立电介质纳米管的半导体器件及其制造方法。在所公开的制造流程中提出了促进催化剂的使用，其促进了形成用于ILD的全部或部分电介质材料的超低k值的直立电介质纳米管的生长。在一个实施方案中，碳纳米管形成层间导电通孔。在另一个实施例中，电介质材料纳米管形成增强柱。提出了催化剂的整合以适应相同层中的直立电介质和直立导电纳米管制造。

5. 发明授权

US07579282B2 Method for removing metal foot during high-k dielectric/metal gate etching 有权
标题翻译：在高k电介质/金属栅极蚀刻期间去除金属脚的方法
公开(公告)号：US07579282B2
公开(公告)日：2009-08-25
申请号：US11331786
申请日：2006-01-13
申请人： Shahid Rauf , Olubunmi O. Adetutu , Eric D. Luckowski , Peter L. G. Ventzek
发明人： Shahid Rauf , Olubunmi O. Adetutu , Eric D. Luckowski , Peter L. G. Ventzek
IPC分类号： H01L21/285 , H01L21/3065
CPC分类号： H01L21/02071 , H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).
摘要翻译：金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82））。接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95）（80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。

6. 发明授权

US07449414B2 Method of treating a mask layer prior to performing an etching process 有权
标题翻译：在进行蚀刻处理之前处理掩模层的方法
公开(公告)号：US07449414B2
公开(公告)日：2008-11-11
申请号：US11499678
申请日：2006-08-07
申请人： Peter L. G. Ventzek , Lee Chen , Akira Koshiishi , Ikuo Sawada
发明人： Peter L. G. Ventzek , Lee Chen , Akira Koshiishi , Ikuo Sawada
IPC分类号： H01L21/302
CPC分类号： H05H1/44 , B05D1/32 , B05D1/62 , B05D3/145 , H01J37/32027 , H01J37/32036 , H01J37/32082 , H01L21/0273 , H01L21/0337 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with a hydrocarbon chemistry or hydrofluorocarbon chemistry or fluorocarbon chemistry or combination of two or more thereof prior to proceeding with the etching process.
摘要翻译：描述了在蚀刻下面的薄膜之前对掩模层进行预处理的方法。使用通过弹道电子束增强的等离子体蚀刻诸如电介质膜的薄膜。为了减少图案定义的损失，例如线边缘粗糙度效应，在进行蚀刻工艺之前，用烃化学或氢氟烃化学或碳氟化合物或其两种或更多种的组合处理掩模层。

7. 发明授权

US06500315B1 Method and apparatus for forming a layer on a substrate 失效
标题翻译：在基板上形成层的方法和装置
公开(公告)号：US06500315B1
公开(公告)日：2002-12-31
申请号：US09631400
申请日：2000-08-03
申请人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
发明人： Valli Arunachalam , Peter L. G. Ventzek , Dean J. Denning , John C. Arnold
IPC分类号： C23C1600
CPC分类号： H01J37/321 , C23C14/352 , C23C14/358 , H01L21/02112 , H01L21/02266 , H01L21/31629
摘要： A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).
摘要翻译：公开了一种在衬底上形成层的方法和装置。根据一个实施例，将衬底（901）放置在包括线圈（16）和屏蔽（14）的腔室（30）中，其中线圈和屏蔽件通过隔离/支撑构件（32）电隔离，具有与所述线圈的表面基本相邻的第一表面（321），并具有与所述屏蔽件的表面基本相邻的第二表面（322）。然后在衬底（901）上沉积一层（1002,1102）。

8. 发明授权

US08808496B2 Plasma tuning rods in microwave processing systems 有权
标题翻译：微波处理系统中的等离子体调谐棒
公开(公告)号：US08808496B2
公开(公告)日：2014-08-19
申请号：US13249485
申请日：2011-09-30
申请人： Jianping Zhao , Lee Chen , Merritt Funk , Toshihiko Iwao , Peter L. G. Ventzek
发明人： Jianping Zhao , Lee Chen , Merritt Funk , Toshihiko Iwao , Peter L. G. Ventzek
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306 , H01J37/32
CPC分类号： H01J37/32192 , H01J37/32247 , H01J37/32256 , Y10T29/49002
摘要： The invention provides a plurality of plasma tuning rod subsystems. The plasma tuning rod subsystems can comprise one or more microwave cavities configured to couple electromagnetic (EM) energy in a desired EM wave mode to a plasma by generating resonant microwave energy in one or more plasma tuning rods within and/or adjacent to the plasma. One or more microwave cavity assemblies can be coupled to a process chamber, and can comprise one or more tuning spaces/cavities. Each tuning space/cavity can have one or more plasma tuning rods coupled thereto. Some of the plasma tuning rods can be configured to couple the EM energy from one or more of the resonant cavities to the process space within the process chamber and thereby create uniform plasma within the process space.
摘要翻译：本发明提供了多个等离子体调谐棒子系统。等离子体调谐杆子系统可以包括一个或多个微波空腔，其被配置为通过在等离子体内和/或邻近等离子体中的一个或多个等离子体调谐杆中产生共振微波能量将所期望的EM波模式中的电磁（EM）能量耦合到等离子体。一个或多个微波空腔组件可以耦合到处理室，并且可以包括一个或多个调谐空间/空腔。每个调谐空间/空腔可以具有耦合到其上的一个或多个等离子体调谐杆。等离子体调谐棒中的一些可被配置为将EM能量从一个或多个谐振腔耦合到处理室内的处理空间，从而在工艺空间内产生均匀的等离子体。

9. 发明授权

US08409459B2 Hollow cathode device and method for using the device to control the uniformity of a plasma process 有权
标题翻译：空心阴极器件和使用该器件来控制等离子体工艺的均匀性的方法
公开(公告)号：US08409459B2
公开(公告)日：2013-04-02
申请号：US12039236
申请日：2008-02-28
申请人： Kazuki Denpoh , Peter L G Ventzek , Lin Xu , Lee Chen
发明人： Kazuki Denpoh , Peter L G Ventzek , Lin Xu , Lee Chen
IPC分类号： H01L21/306
CPC分类号： H01L21/02 , C23C16/45563 , C23C16/45565 , C23C16/50 , C23C16/505 , C23C16/509 , C23C16/5096 , H01J31/00 , H01J37/3244 , H01J37/32596
摘要： A chamber component configured to be coupled to a processing chamber is described. The chamber component comprises one or more adjustable gas passages through which a process gas is introduced to the process chamber. The adjustable gas passage may be configured to form a hollow cathode that creates a hollow cathode plasma in a hollow cathode region having one or more plasma surfaces in contact with the hollow cathode plasma. Therein, at least one of the one or more plasma surfaces is movable in order to vary the size of the hollow cathode region and adjust the properties of the hollow cathode plasma. Furthermore, one or more adjustable hollow cathodes may be utilized to adjust a plasma process for treating a substrate.
摘要翻译：描述了被配置为联接到处理室的室部件。腔室部件包括一个或多个可调节的气体通道，工艺气体通过该气体通道被引入到处理室。可调节气体通道可以被配置成形成空心阴极，该中空阴极在中空阴极区域中形成中空阴极等离子体，其具有与空心阴极等离子体接触的一个或多个等离子体表面。其中，一个或多个等离子体表面中的至少一个可移动以便改变中空阴极区域的尺寸并调节中空阴极等离子体的性质。此外，可以使用一个或多个可调整的中空阴极来调节用于处理衬底的等离子体工艺。

10. 发明申请

US20120258606A1 E-Beam Enhanced Decoupled Source for Semiconductor Processing 有权
标题翻译：用于半导体处理的电子束增强去耦源
公开(公告)号：US20120258606A1
公开(公告)日：2012-10-11
申请号：US13356962
申请日：2012-01-24
申请人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Jun Shinagawa , Akira Koshiishi
发明人： John Patrick Holland , Peter L. G. Ventzek , Harmeet Singh , Jun Shinagawa , Akira Koshiishi
IPC分类号： H01L21/26 , H01L21/3065
CPC分类号： H01J37/32357 , H01J37/32376 , H01J37/32449 , H01J37/32596
摘要： A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes an electron injection device for injecting electrons into the processing chamber to control an electron energy distribution within the processing chamber so as to in turn control an ion-to-radical density ratio within the processing chamber. In one embodiment, an electron beam source is defined to transmit an electron beam through the processing chamber above and across the substrate support.
摘要翻译：半导体基板处理系统包括处理室和限定为在处理室中支撑基板的基板支撑件。该系统还包括与处理室分开限定的等离子体室。等离子体室被定义为产生等离子体。该系统还包括将等离子体室流体连接到处理室的多个流体传输路径。多个流体传输路径被限定为将等离子体的反应性组分从等离子体室提供给处理室。该系统还包括用于将电子注入到处理室中以控制处理室内的电子能量分布的电子注入装置，从而控制处理室内的离子 - 自由基密度比。在一个实施例中，电子束源被定义为将电子束透过衬底支撑件上方并穿过衬底支撑件的处理室。

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