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1. 发明授权

US08093084B2 Semiconductor device with photonics 有权
标题翻译：具有光子学的半导体器件
公开(公告)号：US08093084B2
公开(公告)日：2012-01-10
申请号：US12433431
申请日：2009-04-30
申请人： Gregory S. Spencer , Jill C. Hildreth , Robert E. Jones
发明人： Gregory S. Spencer , Jill C. Hildreth , Robert E. Jones
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , H01L21/76283 , H01L27/1203 , H01L31/028 , H01L31/112
摘要： A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.
摘要翻译：一种用于形成具有晶体管区域和光学器件区域的半导体结构的方法包括在半导体结构的第一半导体层中及其上形成晶体管，其中第一半导体层在第一绝缘层之上，第一绝缘层结束第二半导体层，并且所述第二半导体层在第二绝缘层之上，其中所述晶体管的栅极电介质与所述第一半导体层的顶表面物理接触，并且其中所述晶体管形成在所述晶体管的晶体管区域中半导体结构。该方法还包括在光学器件区域中形成波导器件，其中形成波导器件包括将光学器件区域中的第二半导体层的一部分曝光; 并且在第二半导体层的暴露部分上外延生长第三半导体层。

2. 发明申请

US20110223706A1 METHOD OF FORMING A PHOTODETECTOR 审中-公开
标题翻译：形成光电转换器的方法
公开(公告)号：US20110223706A1
公开(公告)日：2011-09-15
申请号：US12721278
申请日：2010-03-10
申请人： JILL C. HILDRETH , Stanley M. Filipiak , Marc A. Rossow , Gregory S. Spencer , Bret T. Wilkerson
发明人： JILL C. HILDRETH , Stanley M. Filipiak , Marc A. Rossow , Gregory S. Spencer , Bret T. Wilkerson
IPC分类号： H01L31/18
CPC分类号： H01L31/1812 , H01L31/028 , Y02E10/547
摘要： A photodetector is formed to have a germanium detector on a waveguide. The germanium detector has a first surface on the waveguide and a second surface that, when exposed to ambient conditions, forms germanium oxide. In a processing platform, an oxygen-free plasma is applied to the second surface. The oxygen-free plasma removes oxygen that is bonded to germanium at the second surface. A cap layer is formed on the second surface prior to removing the germanium detector from the processing platform.
摘要翻译：光电检测器形成为在波导上具有锗检测器。锗探测器具有波导上的第一表面和暴露于环境条件时形成氧化锗的第二表面。在处理平台中，将无氧等离子体施加到第二表面。无氧等离子体去除在第二表面与锗结合的氧。在从处理平台移除锗检测器之前，在第二表面上形成盖层。

3. 发明授权

US07846803B2 Multiple millisecond anneals for semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的多毫秒退火
公开(公告)号：US07846803B2
公开(公告)日：2010-12-07
申请号：US11756197
申请日：2007-05-31
申请人： Gregory S. Spencer , Vishal P. Trivedi
发明人： Gregory S. Spencer , Vishal P. Trivedi
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/324 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.
摘要翻译：在一个实施例中，形成掺杂区域的方法包括：将掺杂剂注入到半导体衬底中的区域中，通过执行第一毫秒退火使该区域再结晶，其中第一毫秒退火具有第一温度和第一停留时间，以及在重新区域之后使用第二毫秒退火来激活该区域，其中第二毫秒退火具有第二温度和第二停留时间。在一个实施例中，第一毫秒退火和第二毫秒退火使用激光。在一个实施例中，第一温度与第二温度相同，并且第一停留时间与第二停留时间相同。在另一实施例中，第一温度与第二温度不同，第一停留时间不同于第二停留时间。

4. 发明申请

US20080274595A1 Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation 有权
标题翻译：使用氧化硅外延隔离层形成的SOI集成上的双衬底取向或体积
公开(公告)号：US20080274595A1
公开(公告)日：2008-11-06
申请号：US11742778
申请日：2007-05-01
申请人： Gregory S. Spencer , John M. Grant , Gauri V. Karve
发明人： Gregory S. Spencer , John M. Grant , Gauri V. Karve
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96). In this way, SOI sidewall oxide spacers (94) are formed that prevent epitaxial SOI sidewalls from being formed in the trench opening (93) during the epitaxial growth step, and that can be readily removed during any subsequent STI etch process
摘要翻译：半导体工艺和装置通过在沟槽开口（93）中热氧化SOI侧壁（90）来提供平坦化的混合衬底（15），以形成SOI侧壁氧化物间隔物（94），其在蚀刻通过掩埋氧化物层（80）时被修整，以暴露下面的体基板（70），用于外延半导体层（96）的后续外延生长。以这种方式，形成了在外延生长步骤期间防止在沟槽开口（93）中形成外延SOI侧壁的SOI侧壁氧化物间隔物（94），并且可以在任何后续STI蚀刻工艺期间容易地去除

5. 发明授权

US07416605B2 Anneal of epitaxial layer in a semiconductor device 有权
标题翻译：在半导体器件中退火外延层
公开(公告)号：US07416605B2
公开(公告)日：2008-08-26
申请号：US11620987
申请日：2007-01-08
申请人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
发明人： Stefan Zollner , Veeraraghavan Dhandapani , Paul A. Grudowski , Gregory S. Spencer
IPC分类号： C30B25/14 , C30B25/12
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译：包含IV族元素组合的外延生长的晶体半导体层的退火。该层含有碳和锡中的至少一种。外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。退火例如通过激光退火或闪光灯退火来进行。有限时间退火可以改善晶体管的载流子迁移率。

6. 发明授权

US06992003B2 Integration of ultra low K dielectric in a semiconductor fabrication process 失效
标题翻译：在半导体制造工艺中集成超低K电介质
公开(公告)号：US06992003B2
公开(公告)日：2006-01-31
申请号：US10659885
申请日：2003-09-11
申请人： Gregory S. Spencer , Kurt H. Junker , Jason A. Vires
发明人： Gregory S. Spencer , Kurt H. Junker , Jason A. Vires
IPC分类号： H01L21/302
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L21/3122 , H01L21/31633 , H01L21/76832
摘要： A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K
摘要翻译：后端半导体制造工艺包括通过在晶片的衬底上形成覆盖在低K电介质上的有机氧化硅胶层而形成覆盖在晶片衬底上的层间电介质（ILD），形成覆盖晶片衬底的低K电介质（K <3.0），以及形成覆盖胶层电介质的CMP阻挡层电介质。然后在ILD中形成空隙，沉积导电材料以填充空隙，并且抛光工艺除去过量的导电材料。通过使用有机前体和氧前体形成CVD等离子体并且通过形成胶层电介质和停止层来保持等离子体来实现形成胶层电介质和CMP停止层电介质。有机前体的流速相对于氧气前体流速减小以形成基本上不含碳的CMP停止层。

7. 发明申请

US20120080730A1 SEMICONDUCTOR DEVICE WITH PHOTONICS 有权
标题翻译：具有光电子的半导体器件
公开(公告)号：US20120080730A1
公开(公告)日：2012-04-05
申请号：US13313806
申请日：2011-12-07
申请人： GREGORY S. SPENCER , Jill C. Hldreth , Robert E. Jones
发明人： GREGORY S. SPENCER , Jill C. Hldreth , Robert E. Jones
IPC分类号： H01L31/113
CPC分类号： G02B6/12004 , H01L21/76283 , H01L27/1203 , H01L31/028 , H01L31/112
摘要： A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.
摘要翻译：具有晶体管区域和光学器件区域的半导体结构包括在半导体结构的第一半导体层中的晶体管，其中第一半导体层在第一绝缘层之上，第一绝缘层在第二半导体层上，并且第二半导体层在第二绝缘层之上。晶体管的栅极电介质与第一半导体层的顶表面物理接触，并且晶体管形成在半导体结构的晶体管区域中。光学器件区域中的波导器件和第二半导体层的一部分上的第三半导体层。

8. 发明申请

US20110027950A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR 审中-公开
标题翻译：用于形成具有光电转换器的半导体器件的方法
公开(公告)号：US20110027950A1
公开(公告)日：2011-02-03
申请号：US12510358
申请日：2009-07-28
申请人： Robert E. Jones , Dean J. Denning , Gregory S. Spencer
发明人： Robert E. Jones , Dean J. Denning , Gregory S. Spencer
IPC分类号： H01L27/12
CPC分类号： H01L27/14689 , H01L27/0617 , H01L27/14643
摘要： A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material.
摘要翻译：提供了一种用于将锗光电检测器与CMOS电路集成的方法。该方法包括：在硅衬底中形成第一和第二隔离区; 在所述第一隔离区域中形成栅电极; 在邻近栅电极的硅衬底中注入源极/漏极延伸部分; 在所述栅电极上形成第一侧壁间隔物; 在硅衬底中注入源/漏区; 从所述栅极电极去除所述第一侧壁间隔物; 在所述第一和第二隔离区域上形成第一保护层; 去除所述第一保护层的一部分以在所述第二隔离区域上形成开口; 在开口中形成包含锗的半导体材料; 在所述第一和第二隔离区域上形成第二保护层; 从第一隔离区选择性地去除第一和第二保护层; 以及形成与晶体管和半导体材料的接触。

9. 发明授权

US07871854B1 Method of making a vertical photodetector 有权
标题翻译：制造垂直光电探测器的方法
公开(公告)号：US07871854B1
公开(公告)日：2011-01-18
申请号：US12543619
申请日：2009-08-19
申请人： Gregory S. Spencer , Robert E. Jones
发明人： Gregory S. Spencer , Robert E. Jones
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.
摘要翻译：一种方法包括在半导体衬底的顶表面中形成第一开口，在顶表面中进行注入以形成掺杂区域，沿着第一开口的底部沿着第一开口的底部外延生长第一开口中的半导体层，第一开口，其中所述外延生长包括原位掺杂半导体层，用电介质材料填充第一开口，在电介质材料中形成第二开口，其中第二开口的底部露出外延生长的半导体层和侧壁第二开口暴露电介质材料; 以及用半导体材料填充所述第二开口，其中所述半导体材料包括顶部电极和底部电极。底部电极与与掺杂区域电接触的半导体层电接触。掺杂区域横向邻近半导体材料。

10. 发明授权

US07754587B2 Silicon deposition over dual surface orientation substrates to promote uniform polishing 有权
标题翻译：硅沉积在双面取向基板上以促进均匀抛光
公开(公告)号：US07754587B2
公开(公告)日：2010-07-13
申请号：US11375796
申请日：2006-03-14
申请人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka
发明人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/7842 , H01L21/0237 , H01L21/02381 , H01L21/02433 , H01L21/02439 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02516 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/66651 , H01L29/7848
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline silicon (101, 103) over the nitride mask layer (95). The polysilicon material (101, 103) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface (100) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes (151) over a first SOI layer (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon layer (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和装置通过选择性地沉积外延硅层（70）以填充沟槽（96）并且然后将硅覆盖整个晶片以覆盖晶体硅的近均匀厚度（102）而提供平面化的混合衬底（16））超过氮化物掩模层（95）上的外延硅层（70）和多晶硅（101,103）。通过两步法加入的多晶硅材料（101,103）增加后续CMP抛光的抛光速率，从而在整个晶片表面上提供更均匀的抛光表面（100），而不管结构宽度和器件密度的变化。通过使用沉积（100）硅并在外延生长（110）硅层（70）上形成第二栅电极（161）在第一SOI层（90）上形成第一栅电极（151），获得高性能CMOS器件其包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）。

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