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1. 发明申请

US20110078478A1 METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY 有权
标题翻译：基于活动请求频率的功率状态之间的设备转换方法和装置
公开(公告)号：US20110078478A1
公开(公告)日：2011-03-31
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

2. 发明授权

US06954466B1 Link-layer receiver 有权
标题翻译：链路层接收机
公开(公告)号：US06954466B1
公开(公告)日：2005-10-11
申请号：US10457175
申请日：2003-06-09
申请人： Anthony Dalleggio , Denis Rystsov
发明人： Anthony Dalleggio , Denis Rystsov
IPC分类号： H04L12/56 , H04L12/66
CPC分类号： H04L49/90
摘要： A System Packet Interface (SPI) level 4 receiver groups four consecutive 16 bit control/data words into a single 64 bit word (with a resultant rate of up to 210 MHz). The 64 bit word is processed for storage in a dual memory structure comprising two first-in-first-out (FIFO) memories for storing 64 bit words, wherein the 64 bit word may be stored in one, or both, of the FIFOs. The SPI-4.2 receiver issues commands that control subsequent processing of the 64 bit words (e.g., for alignment) using three types of commands, which are based on the relative temporal position of control words in the received data. Temporally, these commands are characterized as: PRE-COMMANDS, POST-COMMANDS and PRESENT-COMMANDS. A parallel general and selection method (PGSM) is used for FIFO Write Command Generation and for Diagonally Interleaved Parity (DIP-4) checking.
摘要翻译：系统分组接口（SPI）4级接收机将四个连续的16位控制/数据字组合成单个64位字（合成速率高达210 MHz）。处理64位字以存储在双存储器结构中，包括两个用于存储64位字的先进先出（FIFO）存储器，其中64位字可以存储在FIFO中的一个或两者中。 SPI-4.2接收机发出使用三种类型的命令来控制64位字的后续处理（例如，用于对准）的命令，这些命令基于接收数据中的控制字的相对时间位置。这些命令暂时表征为：PRE-COMMANDS，POST-COMMANDS和PRESENT-COMMANDS。用于FIFO写入命令生成和对角线交错奇偶校验（DIP-4）检查的并行通用和选择方法（PGSM）。

3. 发明授权

US08112648B2 Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state 有权
标题翻译：加强对CPU驻留和线程重新调度的控制，以最大限度地发挥低功耗状态的优势
公开(公告)号：US08112648B2
公开(公告)日：2012-02-07
申请号：US12333744
申请日：2008-12-12
申请人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
发明人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
IPC分类号： G06F1/26
CPC分类号： G06F9/5027 , G06F1/3203 , G06F1/3296 , G06F9/5094 , G06F2209/508 , Y02D10/172 , Y02D10/22
摘要： A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
摘要翻译：系统可以包括多个处理单元和被配置为维护每个相应处理单元的记录的调度器。每个相应的记录可以包括可以指示1）各个处理单元已经驻留在空闲状态多长时间的条目，2）相应处理单元驻留的当前功率状态，以及3）各个处理单元是否为指定默认（bootstrap）处理单元。调度器可以根据它们各自的记录来选择多个处理单元中的一个或多个，并分配要在所选择的一个或多个处理单元上执行的即将发生的指令。在需要附加处理单元的情况下，调度器还可以插入用于触发处理器间中断以将一个或多个处理单元转变为空闲状态的指令。然后，调度器可以向这些一个或多个处理单元分配一些即将发生的指令。

4. 发明授权

US08291249B2 Method and apparatus for transitioning devices between power states based on activity request frequency 有权
标题翻译：基于活动请求频率在设备状态之间转换设备的方法和装置
公开(公告)号：US08291249B2
公开(公告)日：2012-10-16
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

5. 发明授权

US08001409B2 Synchronization device and methods thereof 有权
标题翻译：同步装置及其方法
公开(公告)号：US08001409B2
公开(公告)日：2011-08-16
申请号：US11750443
申请日：2007-05-18
申请人： Michael J. Osborn , Mark D. Hummel , Denis Rystsov
发明人： Michael J. Osborn , Mark D. Hummel , Denis Rystsov
IPC分类号： G06F1/12
CPC分类号： G06F5/06
摘要： A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.
摘要翻译：一个设备包括不同的时钟域。每个时钟域与不同的时钟信号同步，时钟域之间的数据传输通过FIFO存储器进行。确定哪个时钟域具有较慢的时钟频率，并且选择与较慢时钟相关联的时钟域以生成用于在两个时钟域中访问FIFO存储器的指针。因此，这些指针用于在FIFO存储器中读取和写入数据，从而在时钟域之间传输数据。由于用于数据传输的指针由与较慢时钟相关联的时钟域产生并提供，因此减少了在时钟域之间传送指针所产生的延迟。

6. 发明申请

US20090235260A1 Enhanced Control of CPU Parking and Thread Rescheduling for Maximizing the Benefits of Low-Power State 有权
标题翻译：增强CPU驻留和线程重新调度的控制，以最大限度地发挥低功耗状态的优势
公开(公告)号：US20090235260A1
公开(公告)日：2009-09-17
申请号：US12333744
申请日：2008-12-12
申请人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
发明人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/5027 , G06F1/3203 , G06F1/3296 , G06F9/5094 , G06F2209/508 , Y02D10/172 , Y02D10/22
摘要： A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
摘要翻译：系统可以包括多个处理单元和被配置为维护每个相应处理单元的记录的调度器。每个相应的记录可以包括可以指示1）各个处理单元已经驻留在空闲状态多长时间的条目，2）相应处理单元驻留的当前功率状态，以及3）各个处理单元是否为指定默认（bootstrap）处理单元。调度器可以根据它们各自的记录来选择多个处理单元中的一个或多个，并分配要在所选择的一个或多个处理单元上执行的即将发生的指令。在需要附加处理单元的情况下，调度器还可以插入用于触发处理器间中断以将一个或多个处理单元转变为空闲状态的指令。然后，调度器可以向这些一个或多个处理单元分配一些即将发生的指令。

7. 发明申请

US20080288805A1 SYNCHRONIZATION DEVICE AND METHODS THEREOF 有权
标题翻译：同步装置及其方法
公开(公告)号：US20080288805A1
公开(公告)日：2008-11-20
申请号：US11750443
申请日：2007-05-18
申请人： Michael J. Osborn , Mark D. Hummel , Denis Rystsov
发明人： Michael J. Osborn , Mark D. Hummel , Denis Rystsov
IPC分类号： G06F1/12
CPC分类号： G06F5/06
摘要： A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined which clock domain has a slower clock frequency, and the clock domain associated with the slower clock is selected to generate pointers used to access the FIFO memory in both clock domains. Therefore, the pointers are used to read and write data at the FIFO memory resulting in a transfer of the data between the clock domains. Because the pointers used for data transfer are generated and provided by the clock domain associated with the slower clock, the latency resulting from transferring the pointer between the clock domains is reduced.
摘要翻译：一个设备包括不同的时钟域。每个时钟域与不同的时钟信号同步，时钟域之间的数据传输通过FIFO存储器进行。确定哪个时钟域具有较慢的时钟频率，并且选择与较慢时钟相关联的时钟域以生成用于在两个时钟域中访问FIFO存储器的指针。因此，这些指针用于在FIFO存储器中读取和写入数据，从而在时钟域之间传输数据。由于用于数据传输的指针由与较慢时钟相关联的时钟域产生并提供，因此减少了在时钟域之间传送指针所产生的延迟。

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