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1. 发明申请

US20110078478A1 METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY 有权
标题翻译：基于活动请求频率的功率状态之间的设备转换方法和装置
公开(公告)号：US20110078478A1
公开(公告)日：2011-03-31
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

2. 发明授权

US08291249B2 Method and apparatus for transitioning devices between power states based on activity request frequency 有权
标题翻译：基于活动请求频率在设备状态之间转换设备的方法和装置
公开(公告)号：US08291249B2
公开(公告)日：2012-10-16
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

3. 发明授权

US5638538A Turbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system bus 失效
标题翻译：可触发的：用于在耦合到流水线系统总线的节点上的多个消费者之间指导地址和命令的装置
公开(公告)号：US5638538A
公开(公告)日：1997-06-10
申请号：US372533
申请日：1995-01-13
申请人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
发明人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
IPC分类号： G06F13/36 , G06F13/00 , G06F12/00
CPC分类号： G06F13/36
摘要： A command queueing apparatus for directing address and command information amongst the various interfaces, or consumers, on a multi-CPU node in a computer system. The apparatus includes a core queue containing core queue entries, each core queue entry corresponding to a pending system bus operation. Each core queue entry includes one or more consumer information fields specific to each consumer. Also included is a plurality of virtual queues, each virtual queue corresponding to a consumer, each virtual queue having a virtual queue entry. A virtual queue entry for a consumer is a subset of the fields of a core queue entry, the subset of fields including the consumer information fields for the consumer corresponding to the virtual queue.
摘要翻译：一种用于在计算机系统中的多CPU节点上指导各种接口或消费者之间的地址和命令信息的命令排队装置。该装置包括一个包含核心队列条目的核心队列，每个核心队列条目对应于待处理的系统总线操作。每个核心队列条目包括每个消费者特有的一个或多个消费者信息字段。还包括多个虚拟队列，每个虚拟队列对应于消费者，每个虚拟队列具有虚拟队列条目。消费者的虚拟队列条目是核心队列条目的字段的子集，字段的子集包括与虚拟队列对应的消费者的消费者信息字段。

4. 发明授权

US09043625B2 Processor bridge power management 有权
标题翻译：处理器桥电源管理
公开(公告)号：US09043625B2
公开(公告)日：2015-05-26
申请号：US13446030
申请日：2012-04-13
申请人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
发明人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3253 , G06F1/3296 , Y02D10/151 , Y02D10/172
摘要： A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.
摘要翻译：功率控制器可以基于哪个处理器模块处于通信状态来设置处理器网桥的电源状态。另外，对于预期选择的处理器模块是不通信的电源状态，功率控制器可以将所提供的电压设置为与其它功率状态相比具有降低的电压保护带。这些电源管理技术可以减少处理器消耗的功耗。

5. 发明申请

US20130275778A1 PROCESSOR BRIDGE POWER MANAGEMENT 有权
标题翻译：加工车桥电源管理
公开(公告)号：US20130275778A1
公开(公告)日：2013-10-17
申请号：US13446030
申请日：2012-04-13
申请人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
发明人： Maurice B. Steinman , Alexander J. Branover , Denis J. Foley , Ljubisa Bajic
IPC分类号： G06F1/26
CPC分类号： G06F1/3253 , G06F1/3296 , Y02D10/151 , Y02D10/172
摘要： A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.
摘要翻译：功率控制器可以基于哪个处理器模块处于通信状态来设置处理器网桥的电源状态。另外，对于预期选择的处理器模块是不通信的电源状态，功率控制器可以将所提供的电压设置为与其它功率状态相比具有降低的电压保护频带。这些电源管理技术可以减少处理器消耗的功耗。

6. 发明授权

US6076129A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US6076129A
公开(公告)日：2000-06-13
申请号：US869610
申请日：1997-06-06
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means for tracking producing a sequence number tag corresponding to each address and command transaction occurring on the address bus. Means for associating data transactions with address and command transactions stores the sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node. Further included are means for tracking data transactions occurring on a data bus, means for comparing tracked data transactions to associated data transactions, and means for initiating data transactions on the data bus in response to the comparison. The data bus sequencer further includes means for driving the sequence tag for an address and command transaction to which a data transaction is associated on the data bus. Consistency check means includes means for tracking data transactions occurring on a data bus, and means for comparing tracked data transactions to sequence number tags driven on the data bus. The consistency check means indicates an error condition in response to the comparison if the sequence number tag most recently driven on the data bus is not equal to the counted number of data transactions which have occurred on the data bus.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。数据总线定序器包括用于跟踪在地址总线上发生的地址和命令事务的装置，用于跟踪的装置产生对应于地址总线上发生的每个地址和命令事务的序列号标签。用于将数据事务与地址和命令事务相关联的手段存储对应于由节点发起数据事务的地址和命令事务的序列号标签。还包括用于跟踪在数据总线上发生的数据交易的装置，用于将跟踪的数据交易与相关联的数据交易进行比较的装置，以及用于响应于比较在数据总线上启动数据交易的装置。数据总线序列器还包括用于驱动序列标签的装置，用于在数据总线上与数据事务相关联的地址和命令事务。一致性检查装置包括用于跟踪在数据总线上发生的数据交易的装置，以及用于将跟踪的数据事务与在数据总线上驱动的序列号标签进行比较的装置。如果最近在数据总线上驱动的序列号标签不等于在数据总线上发生的数据交易的计数，则一致性检查装置响应于比较来指示错误状况。

7. 发明申请

US20080282006A1 Latency Hiding for a Memory Management Unit Page Table Lookup 有权
标题翻译：内存管理单元的延迟隐藏页表查找
公开(公告)号：US20080282006A1
公开(公告)日：2008-11-13
申请号：US11768375
申请日：2007-06-26
申请人： Anthony F. Vivenzio , Denis J. Foley
发明人： Anthony F. Vivenzio , Denis J. Foley
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F2212/1016
摘要： In certain systems, local request's require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request, is present If the associated information is present, a request is placed in an output request queue to service the local request If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.
摘要翻译：在某些系统中，本地请求需要存在相应的相关信息才能被服务。本地内存存储一些相关信息。与检索关联信息有关的延迟不能立即可用。逻辑操作用于每个本地请求以访问本地存储器，以确定与本地请求相对应的相关信息是否存在如果存在相关联的信息，则请求被放置在输出请求队列中以服务于本地请求。如果相关信息不存在，请求被放置在旁路路径上以检索关联的信息。从旁路路径请求发出优先级超过来自输出请求队列的请求。因此，在相关信息检索的延迟期间可以进行有用的工作。该安排在MMU中的TLB中是有用的。

8. 发明授权

US5666551A Distributed data bus sequencing for a system bus with separate address and data bus protocols 失效
标题翻译：用于具有单独地址和数据总线协议的系统总线的分布式数据总线排序
公开(公告)号：US5666551A
公开(公告)日：1997-09-09
申请号：US590802
申请日：1996-01-24
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , David W. Hartwell , Elbert Bloom , Ricky C. Hetherington
IPC分类号： G06F11/00 , G06F13/42 , G06F13/00
CPC分类号： G06F11/076 , G06F13/4217
摘要： A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.
摘要翻译：数据总线排序器，用于耦合到系统总线的节点，用于将数据事务和总线上的地址事务相关联。用于跟踪在总线上发生的地址和命令事务的机制针对地址总线上发生的每个地址和命令事务产生相应的序列号标签。由数据总线排序器存储与节点发起数据事务的地址和命令事务对应的那些序列号标签。数据总线序列器还包括用于对在数据总线上发生的数据事务的数量进行计数的电路，将计数的数据事务数与存储的序列号标签进行比较，并响应于该比较在数据总线上启动数据事务。

9. 发明授权

US08205064B2 Latency hiding for a memory management unit page table lookup 有权
标题翻译：用于内存管理单元页表查找的延迟隐藏
公开(公告)号：US08205064B2
公开(公告)日：2012-06-19
申请号：US11768375
申请日：2007-06-26
申请人： Anthony F. Vivenzio , Denis J. Foley
发明人： Anthony F. Vivenzio , Denis J. Foley
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1027 , G06F2212/1016
摘要： In certain systems, local requests require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request is present. If the associated information is present, a request is placed in an output request queue to service the local request. If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.
摘要翻译：在某些系统中，本地请求需要存在相应的相关信息才能被服务。本地内存存储一些相关信息。与检索关联信息有关的延迟不能立即可用。逻辑操作用于每个本地请求以访问本地存储器，以确定是否存在与本地请求相对应的相关信息。如果存在相关联的信息，则在输出请求队列中放置请求以服务本地请求。如果相关信息不存在，则请求将放置在旁路路径上以检索相关信息。从旁路路径请求发出优先级超过来自输出请求队列的请求。因此，在相关信息检索的延迟期间可以进行有用的工作。该安排在MMU中的TLB中是有用的。

10. 发明授权

US5737546A System bus with separate address and data bus protocols 失效
标题翻译：系统总线具有独立的地址和数据总线协议
公开(公告)号：US5737546A
公开(公告)日：1998-04-07
申请号：US775552
申请日：1996-12-31
申请人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
发明人： David M. Fenwick , Denis J. Foley , Stephen R. Van Doren , Dale R. Keck
IPC分类号： G06F13/42 , G06F13/00 , G06F13/368
CPC分类号： G06F13/4213
摘要： Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. In particular, the timing of data transactions and the rate at which data transactions occur on the data bus is independent of the timing of address and command transactions and the rate at which address sub-transactions occur on the address bus.
摘要翻译：耦合到计算机系统中的系统总线的节点的总线接口，系统总线包括地址总线和单独的数据总线。系统总线操作包括地址和命令事务和数据事务。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。总线接口可以包括用于向地址总线地址和命令事务提供的指挥官地址总线接口装置中的任一个，用于通过地址总线确认接收地址和命令事务的响应方地址总线接口装置，用于由于在地址总线上发生地址和命令事务而导致数据事务的数据总线的提交;以及响应者数据总线接口装置，用于在数据事务期间在数据总线上传送数据。在数据总线上分别发生数据事务，与地址总线上地址和命令事务的发生无关。特别地，数据事务的定时和数据事务在数据总线上发生的速率与地址和命令事务的定时以及地址总线上发生地址子事务的速率无关。

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