专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08291249B2 Method and apparatus for transitioning devices between power states based on activity request frequency 有权
标题翻译：基于活动请求频率在设备状态之间转换设备的方法和装置
公开(公告)号：US08291249B2
公开(公告)日：2012-10-16
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

2. 发明申请

US20110078478A1 METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY 有权
标题翻译：基于活动请求频率的功率状态之间的设备转换方法和装置
公开(公告)号：US20110078478A1
公开(公告)日：2011-03-31
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

3. 发明授权

US08112648B2 Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state 有权
标题翻译：加强对CPU驻留和线程重新调度的控制，以最大限度地发挥低功耗状态的优势
公开(公告)号：US08112648B2
公开(公告)日：2012-02-07
申请号：US12333744
申请日：2008-12-12
申请人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
发明人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
IPC分类号： G06F1/26
CPC分类号： G06F9/5027 , G06F1/3203 , G06F1/3296 , G06F9/5094 , G06F2209/508 , Y02D10/172 , Y02D10/22
摘要： A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
摘要翻译：系统可以包括多个处理单元和被配置为维护每个相应处理单元的记录的调度器。每个相应的记录可以包括可以指示1）各个处理单元已经驻留在空闲状态多长时间的条目，2）相应处理单元驻留的当前功率状态，以及3）各个处理单元是否为指定默认（bootstrap）处理单元。调度器可以根据它们各自的记录来选择多个处理单元中的一个或多个，并分配要在所选择的一个或多个处理单元上执行的即将发生的指令。在需要附加处理单元的情况下，调度器还可以插入用于触发处理器间中断以将一个或多个处理单元转变为空闲状态的指令。然后，调度器可以向这些一个或多个处理单元分配一些即将发生的指令。

4. 发明申请

US20090235260A1 Enhanced Control of CPU Parking and Thread Rescheduling for Maximizing the Benefits of Low-Power State 有权
标题翻译：增强CPU驻留和线程重新调度的控制，以最大限度地发挥低功耗状态的优势
公开(公告)号：US20090235260A1
公开(公告)日：2009-09-17
申请号：US12333744
申请日：2008-12-12
申请人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
发明人： Alexander Branover , Maurice B. Steinman , Denis Rystsov
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/5027 , G06F1/3203 , G06F1/3296 , G06F9/5094 , G06F2209/508 , Y02D10/172 , Y02D10/22
摘要： A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
摘要翻译：系统可以包括多个处理单元和被配置为维护每个相应处理单元的记录的调度器。每个相应的记录可以包括可以指示1）各个处理单元已经驻留在空闲状态多长时间的条目，2）相应处理单元驻留的当前功率状态，以及3）各个处理单元是否为指定默认（bootstrap）处理单元。调度器可以根据它们各自的记录来选择多个处理单元中的一个或多个，并分配要在所选择的一个或多个处理单元上执行的即将发生的指令。在需要附加处理单元的情况下，调度器还可以插入用于触发处理器间中断以将一个或多个处理单元转变为空闲状态的指令。然后，调度器可以向这些一个或多个处理单元分配一些即将发生的指令。

5. 发明申请

US20110283124A1 METHOD AND APPARATUS FOR CACHE CONTROL 有权
标题翻译：缓存控制的方法和设备
公开(公告)号：US20110283124A1
公开(公告)日：2011-11-17
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

6. 发明申请

US20110112798A1 CONTROLLING PERFORMANCE/POWER BY FREQUENCY CONTROL OF THE RESPONDING NODE 审中-公开
标题翻译：通过响应节点的频率控制来控制性能/功率
公开(公告)号：US20110112798A1
公开(公告)日：2011-05-12
申请号：US12623997
申请日：2009-11-23
申请人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
发明人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
IPC分类号： G21C17/00
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.
摘要翻译：处理节点跟踪与其内部缓存或存储器系统相关联的探测活动级别。如果探测器活动级别增加到阈值探测器活动级别以上，则处理节点的性能状态将增加到其当前的性能状态以提供增强的响应探测请求的性能能力。响应于探测器活动级别高于阈值探测器活动级别而进入更高性能状态之后，处理节点响应于探测活动的减少而返回到较低的性能状态。可能存在多个阈值探测活动级别和相关的性能状态。

7. 发明授权

US08412971B2 Method and apparatus for cache control 有权
标题翻译：用于缓存控制的方法和装置
公开(公告)号：US08412971B2
公开(公告)日：2013-04-02
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

8. 发明授权

US08566628B2 North-bridge to south-bridge protocol for placing processor in low power state 有权
标题翻译：用于将处理器置于低功率状态的北桥南桥协议
公开(公告)号：US08566628B2
公开(公告)日：2013-10-22
申请号：US12436439
申请日：2009-05-06
申请人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
发明人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.
摘要翻译：处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。北桥还从南桥集成电路获得了第二个功率状态建议。北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

9. 发明授权

US09021209B2 Cache flush based on idle prediction and probe activity level 有权
标题翻译：基于空闲预测和探测活动级别的缓存刷新
公开(公告)号：US09021209B2
公开(公告)日：2015-04-28
申请号：US12702085
申请日：2010-02-08
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.
摘要翻译：处理节点跟踪与其高速缓存相关联的探测活动级别。处理节点和/或处理系统进一步预测空闲持续时间。如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到高于其当前性能状态，以提供响应探测请求的增强的性能能力。

10. 发明授权

US08656198B2 Method and apparatus for memory power management 有权
标题翻译：用于存储器电源管理的方法和装置
公开(公告)号：US08656198B2
公开(公告)日：2014-02-18
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式