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1. 发明授权

US07253689B2 Low distortion amplifier 有权
标题翻译：低失真放大器
公开(公告)号：US07253689B2
公开(公告)日：2007-08-07
申请号：US11148683
申请日：2005-06-08
申请人： Don C. Devendorf , Lloyd F. Linder , Cuong D. Tran
发明人： Don C. Devendorf , Lloyd F. Linder , Cuong D. Tran
IPC分类号： H03F3/04
CPC分类号： H03F1/32 , H03F3/26 , H03F3/3435
摘要： A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.
摘要翻译：低失真放大器。新型放大器包括具有第一和第二输出端的第一晶体管Q 1和适于接收输入信号的输入端，以及具有第一和第二输出端的第二晶体管Q 2和适于从第一和第二输出端接收信号的输入端 Q 1的输出端子，其中Q 1的第二输出端子连接到Q 2的第二输出端子，以消除Q 2中的非线性电流分量。在说明性实施例中，放大器还包括用于将Q1和Q2的第二输出端保持在期望电压的共源共栅达林顿对Q 3，Q 4，以进一步减少失真并维持宽带宽。

2. 发明授权

US06400229B1 Low noise, low distortion RF amplifier topology 有权
标题翻译：低噪声，低失真RF放大器拓扑
公开(公告)号：US06400229B1
公开(公告)日：2002-06-04
申请号：US09790796
申请日：2001-02-22
申请人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
发明人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
IPC分类号： H03F122
CPC分类号： H03F1/34 , H03F1/22 , H03F3/42 , H03F2200/372
摘要： A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2. In the specific illustrative embodiment, the invention further includes a fourth circuit for regulating a rate of change of voltage across the transistor Q1 such that the rate of voltage change is zero. The fourth circuit includes a transistor Q4 connected to the transistor Q1 in cascode. The two diodes D1 and D2 also connect the transistors Q1 and Q4 such that the voltage at the input of the transistor Q4 is modulated in proportion to the voltage modulation at the input of the transistor Q1.
摘要翻译：低噪声，低失真射频放大器，其包括自举设计，以最小化互调失真，同时实现低噪声和宽带宽。在说明性实施例中，本发明包括用于接收输入信号的第一电路; 用于使用晶体管Q2放大输入信号的第二电路; 以及用于调节晶体管Q2两端的电压变化率的第三电路，使得电压变化率为零。第三电路包括以级联连接到晶体管Q2的晶体管Q3。在具体说明性实施例中，第三电路还包括两个二极管D1和D2，用于与晶体管Q2的输入处的电压调制成比例地调制晶体管Q3的输入端的电压。在说明性实施例中，第二电路包括级联连接到晶体管Q2的晶体管Q1。在具体说明性实施例中，本发明还包括用于调节跨越晶体管Q1的电压变化率的第四电路，使得电压变化率为零。第四电路包括以级联连接到晶体管Q1的晶体管Q4。两个二极管D1和D2还连接晶体管Q1和Q4，使得晶体管Q4的输入处的电压与晶体管Q1的输入处的电压调制成比例地调制。

3. 发明授权

US5058107A Efficient digital frequency division multiplexed signal receiver 失效
标题翻译：高效数字频分多址信号接收机
公开(公告)号：US5058107A
公开(公告)日：1991-10-15
申请号：US293894
申请日：1989-01-05
申请人： Wade J. Stone , Kikuo Ichiroku , Edwin A. Kelley , Don C. Devendorf
发明人： Wade J. Stone , Kikuo Ichiroku , Edwin A. Kelley , Don C. Devendorf
IPC分类号： H03D3/00 , H04B1/16 , H04J1/00 , H04J1/05
CPC分类号： H04J1/05
摘要： A digital intermediate frequency (IF) receiver for frequency division multiplexed (FDM) signals including analog circuitry for receiving FDM signals and an analog-to-digital (A/D) converter for converting the received signals to a sampled digital received signal. A digital complex mixer responsive to the digital output of the A/D converter translates the spectrum of the sampled digital received signal to center the desired FDM channel at zero frequency (DC). Digital low pass filtering isolates the desired channel centered at DC, and a digital complex mixer can be used to translate the isolated selected channel to a predetermined IF frequency. The in-phase portion of the digital IF centered selected channel or the DC centered complex envelope selected channel can then be provided to appropriate demodulation or decoder networks.

4. 发明授权

US4229729A Analog to digital converter utilizing a quantizer network 失效
标题翻译：使用量化网络的模数转换器
公开(公告)号：US4229729A
公开(公告)日：1980-10-21
申请号：US907478
申请日：1978-05-19
申请人： Don C. Devendorf , Eugene Baskevitch
发明人： Don C. Devendorf , Eugene Baskevitch
IPC分类号： H03M1/00 , H03K13/175
CPC分类号： H03M1/0872 , H03M1/362
摘要： A quantizer network is disclosed for decoding an analog signal and providing a four-bit digital output. The analog input signal is divided or quantized into sixteen discrete voltage ranges and applied to sixteen differential amplifiers. Each amplifier has a different reference which must be exceeded before it provides an output signal. The sixteen differential amplifiers are connected to nine latch networks which respond to the signals from the amplifiers and provide a cyclic code in response thereto. The latch networks are connected to a network of logic gates which decode the cycle code into a four-bit digital output signal. The output signals from the logic gate network are applied to output stages which extend the valid time of the output signal from the logic gates.
摘要翻译：公开了用于对模拟信号进行解码并提供四位数字输出的量化器网络。模拟输入信号被分割或量化为十六个离散电压范围，并应用于十六个差分放大器。每个放大器在提供输出信号之前必须具有不同的参考值。十六个差分放大器连接到九个锁存网络，其响应来自放大器的信号，并响应于此提供循环码。锁存网络连接到将周期代码解码为四位数字输出信号的逻辑门网络。来自逻辑门网络的输出信号被施加到延长来自逻辑门的输出信号的有效时间的输出级。

5. 发明授权

US07755429B2 System and method for dynamic drain voltage adjustment to control linearity, output power, and efficiency in RF power amplifiers 有权
标题翻译：用于动态漏极电压调整的系统和方法，用于控制RF功率放大器的线性度，输出功率和效率
公开(公告)号：US07755429B2
公开(公告)日：2010-07-13
申请号：US12031249
申请日：2008-02-14
申请人： Dung C. Nguyen , Soon Yoon , Ahmad Khanifar , Don C. Devendorf
发明人： Dung C. Nguyen , Soon Yoon , Ahmad Khanifar , Don C. Devendorf
IPC分类号： H03F3/04
CPC分类号： H03F1/0211 , H03F1/0233 , H03F1/0261 , H03F1/0288 , H03F1/301 , H03F1/32 , H03F3/24 , H03F2200/102 , H03F2200/105 , H03F2200/15 , H03F2200/24 , H03F2200/27 , H03F2200/393 , H03F2200/405 , H03F2200/447 , H03F2200/451 , H03F2200/465 , H03F2200/468 , H03F2200/504 , H03F2200/511 , H03F2200/516
摘要： A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency.
摘要翻译：用于动态调整功率放大器（PA）的漏极或集电极电压的系统和方法，包括具有电压输入的PA，测量PA的环境温度的温度传感器以及动态地改变输入电压的自适应PA控制处理器基于环境温度，当系统经受高温时获得期望的峰值功率。在另一实施例中，功率传感器测量PA的输出功率，并且当系统服务于采用高功率的移动通信基础设施中的大小区时，控制处理器基于输出功率来动态地改变电压。在另一实施例中，多级PA和方法包括具有漏极或集电极电压输入的放大器级，其中施加到输入的电压被设置成与每级的峰值功率要求成比例，从而提高整体效率。

6. 发明授权

US07738573B2 System and method for crest factor reduction 有权
标题翻译：波峰因数降低的系统和方法
公开(公告)号：US07738573B2
公开(公告)日：2010-06-15
申请号：US11246027
申请日：2005-10-07
申请人： Khiem V. Cai , Samuel Davis Kent, III , Don C. Devendorf
发明人： Khiem V. Cai , Samuel Davis Kent, III , Don C. Devendorf
IPC分类号： H04K1/10
CPC分类号： H04L27/2624
摘要： A crest reduction system and method. The inventive system includes a first circuit for suppressing peak amplitudes of an input signal and providing a peak amplitude suppressed signal in response thereto and a second circuit coupled to the first circuit for rejecting intermodulation distortion in the amplitude suppressed signal. In the illustrative implementation, the first circuit is a peak amplitude suppressor having circuitry for computing an amplitude of the input signal and for computing a gain factor for the input signal in response thereto. In the best mode, the gain factor is obtained from a lookup table. The peak amplitude suppressor further includes a multiplier for applying the gain factor to the input signal. In the illustrative embodiment, the second circuit includes a plurality of bandpass filters and a summer for combining the outputs thereof.
摘要翻译：一种降幅系统和方法。本发明的系统包括：第一电路，用于抑制输入信号的峰值振幅并响应于此提供峰值振幅抑制信号;以及第二电路，耦合到第一电路，用于抑制振幅抑制信号中的互调失真。在说明性实现中，第一电路是峰值幅度抑制器，其具有用于计算输入信号的幅度的电路，并且响应于此计算输入信号的增益因子。在最佳模式下，增益因子从查找表获得。峰值幅度抑制器还包括用于将增益因子应用于输入信号的乘法器。在说明性实施例中，第二电路包括多个带通滤波器和用于组合其输出的加法器。

7. 发明申请

US20100020900A1 DIGITAL PRE-DISTORTION TECHNIQUE USING NONLINEAR FILTERS 有权
标题翻译：使用非线性滤波器的数字预失真技术
公开(公告)号：US20100020900A1
公开(公告)日：2010-01-28
申请号：US12574796
申请日：2009-10-07
申请人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
发明人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
IPC分类号： H04L25/49
CPC分类号： H04L25/03885 , H03F1/3247 , H03F1/3276 , H04L25/49 , H04L27/2626 , H04L27/368
摘要： A method and computer program product for operating a linearizer for a circuit, including generating a set of coefficients via a characterizer; predistorting a signal input to the circuit responsive to the coefficients and generating a linearized output in response thereto; filtering the signal through a linear digital filter having linear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; generating powers of the signal; inputting the generated powers of the signal through tapped delay lines, each line having nonlinear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; applying the coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units to a particular linear digital filter tap.
摘要翻译：一种用于操作电路的线性化器的方法和计算机程序产品，包括经由表征器生成一组系数; 响应于系数预失真输入到电路的信号并响应于此产生线性化的输出; 通过具有线性数字滤波器抽头的线性数字滤波器对信号进行滤波，除了连续延迟一个延迟单元的第一抽头以外的每个抽头; 产生信号的功率; 通过抽头延迟线输入信号的发生功率，每行具有非线性数字滤波器抽头，每个抽头不同于连续延迟一个延迟单元的第一抽头; 将系数应用于线性和非线性数字滤波器抽头; 对与一定数量的延迟单元相对应的每个非线性数字滤波器抽头相加; 并将每个延迟单元的和加到特定的线性数字滤波器抽头上。

8. 发明授权

US07154421B2 DNL/INL trim techniques for comparator based analog to digital converters 有权
标题翻译：用于基于比较器的模数转换器的DNL / INL微调技术
公开(公告)号：US07154421B2
公开(公告)日：2006-12-26
申请号：US10890443
申请日：2004-07-12
申请人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
发明人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03M1/06
CPC分类号： H03K5/2418 , H03M1/1057 , H03M1/1061 , H03M1/363
摘要： A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.
摘要翻译：可调整比较器。新颖的比较器包括用于比较第一和第二输入信号并根据其产生第一和第二输出信号的第一电路和用于将可调电流加到第一输出信号的第二电路，使得当比较器处于转换状态时第一和/或第二输入信号处于期望的电平。比较器还可以包括用于将可调电流加到第二输出信号的第三电路。在说明性实施例中，第二和第三电路使用具有可调节电阻器的可调电流源或使用数模转换器来实现。新颖的比较器可以用在模数转换器中以允许将转换器阈值调整到期望的水平。

9. 发明授权

US07098684B2 High speed switch 有权
标题翻译：高速开关
公开(公告)号：US07098684B2
公开(公告)日：2006-08-29
申请号：US10740173
申请日：2003-12-18
申请人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
发明人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
IPC分类号： H03K19/013
CPC分类号： G11C27/02 , H03K17/04113
摘要： A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.
摘要翻译：高速开关新型开关包括具有用于接收输入信号的晶体管Q 1的输入电路，用于提供从Q 1的输出到输出端的路径的第一机构，以及用于接收控制信号的第二机构，并且根据其减少在静音模式下路径的电导率。第一机构包括用于提供从Q1的输出到第一节点的第一路径的第一电路和用于提供将第一节点连接到输出端子的第二路径的第二电路。第二机构适于在静音模式期间将信号施加到第一节点，使得第一和第二电路关闭或部分导通。开关还包括用于在静音模式期间将第一节点钳位到第一预定电压的电路。

10. 发明授权

US06693980B1 Wideband fast-hopping receiver front-end and mixing method 有权
标题翻译：宽带快跳接收机前端和混合方式
公开(公告)号：US06693980B1
公开(公告)日：2004-02-17
申请号：US09664298
申请日：2000-09-18
申请人： Lloyd F. Linder , Don C. Devendorf
发明人： Lloyd F. Linder , Don C. Devendorf
IPC分类号： H04L2722
CPC分类号： H03D7/165
摘要： A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.
摘要翻译：宽带快速跳频接收机前端使用直接数字合成（DDS）向前端的混频器提供正交LO信号。 DDS电路存储表示所需波形的多个数字字序列，并响应于时钟信号和命令信号将期望的序列对输出到一对DAC。 DAC将序列转换为模拟信号，根据需要进行滤波和平方以向混频器提供正交LO信号。通过改变命令信号来实现跳频，这导致输出不同的序列对，并且提供给混频器的LO信号的频率被改变。主动图像抑制与DDS LO生成相结合，提供更快的跳频。前端与ADC和通信信号处理器相结合，提供一个完整的系统，所有系统都可以集成在一个共同的基板上。

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