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    • 3. 发明授权
    • Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer
    • 具有可控加权的并行高通和低通滤波器的均衡器和包括这种均衡器的接收器
    • US08275026B2
    • 2012-09-25
    • US11796175
    • 2007-04-27
    • Dongyun Lee
    • Dongyun Lee
    • H03H7/40
    • H04L25/03159H04L63/04H04L63/166H04L2025/03356H04L2025/03522
    • An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (β), and a second branch including a high pass filter (HPF) and having another variable gain (α). The equalizer can be implemented using CMOS technology so that the gain parameters β and α are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. In some embodiments, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0·(β+α·(1+s·C0·Z0)), where β is a gain parameter determined by the tail current of one differential pair and α is a gain parameter determined by the tail current of the other differential pair.
    • 一种可调均衡器,其包括包括低通滤波器(LPF)并具有可变增益的第一分支(& bgr),以及包括高通滤波器(HPF)并具有另一可变增益(α)的第二分支。 均衡器可以使用CMOS技术实现,使得增益参数&bgr; α是独立可调的,并且均衡器能够均衡指示具有至少1Gb / s的最大数据速率的数据的输入。 在一些实施例中,均衡器包括两个MOS晶体管的差分对,并且可控电流源确定每个差分对的尾电流。 当均衡器包括纯电阻阻抗Z0和Z1时,均衡器的传递函数为Z1 / Z0·(&bgr; +α·(1 + s·C0·Z0)),其中&bgr; 是由一个差分对的尾部电流确定的增益参数,α是由另一个差分对的尾部电流确定的增益参数。
    • 5. 发明授权
    • Multi-port memory device having variable port speeds
    • 具有可变端口速度的多端口存储设备
    • US07639561B2
    • 2009-12-29
    • US11694813
    • 2007-03-30
    • Dongyun LeeMyung Rai ChoSungjoon Kim
    • Dongyun LeeMyung Rai ChoSungjoon Kim
    • G11C8/18
    • G11C8/16G06F13/4054G06F13/4243G11C7/1075G11C2207/108
    • A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
    • 具有两个或多个端口的多端口存储器件,其中每个端口可以以不同的速度操作。 多端口存储器件包含可通过两个或更多个端口访问的存储体。 每个端口都应用两个时钟信号:系统时钟和端口时钟。 系统时钟被应用于与存储体接口的端口逻辑,使得端口都以相对于存储体的公共速度运行。 端口时钟应用于与每个端口相关联的时钟分频器电路。 端口时钟被分为所需频率或保持在其原始频率。 这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。
    • 7. 发明申请
    • SIGNAL INTERLEAVING FOR SERIAL CLOCK AND DATA RECOVERY
    • 用于串行时钟和数据恢复的信号交互
    • US20080075222A1
    • 2008-03-27
    • US11861175
    • 2007-09-25
    • Dongyun LeeSungjoon Kim
    • Dongyun LeeSungjoon Kim
    • H03D3/24H04L7/00
    • H04L7/0337H03L7/07H03L7/0812
    • A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.
    • 一种用于从串行数据流中恢复定时信息和数据的时钟和数据恢复(CDR)系统和方法。 CDR系统包括产生恢复的时钟/数据信号的采样电路和向采样电路提供反馈的交错反馈网络。 反馈网络包括基于恢复的时钟/数据信号产生控制信号的逻辑电路,第一多路复用器,其基于控制信号从全局时钟信号的四相中选择第一延迟锁定环,第一延迟锁定环具有第一组 延迟单元,耦合到第二多路复用器,其基于所选择的全局时钟信号产生延迟的信号;以及第二延迟锁定环,其具有产生一组相移反馈信号的第二组延迟单元,所述相移反馈信号被施加到采样 电路使采样电路与接收到的串行数据流中的转换相对齐。
    • 8. 发明授权
    • Heat sink assembly incorporating spring clip
    • 散热器组件结合弹簧夹
    • US07203066B2
    • 2007-04-10
    • US10901513
    • 2004-07-28
    • Hsieh Kun LeeDongyun LeeZhijie ZhangHong Bo Shi
    • Hsieh Kun LeeDongyun LeeZhijie ZhangHong Bo Shi
    • G06F1/20
    • H01L23/4093H01L2924/0002H01L2924/00
    • A heat sink assembly includes a heat sink (20) and a pair of clips (10) attached on opposite sides of the heat sink for securing the heat sink to an electronic component (40). The heat sink includes a base (22) and a plurality of fins (24). A pair of protrusions (28) is formed on bottom portions of adjacent two fins. A locking slot (29) is therefore formed between the base, the two adjacent fins, and the protrusions. The clip includes a pressing portion (12) squeenzedly received in the locking slot, a pair of extension portions (14) extending from opposite ends of the pressing portion, and a pair of hooks (16) formed on free ends of the extension portions. When the clips are deformed to cause the hooks to engage with the electronic component, the pressing portions of the clips press the heat sink toward the electronic component.
    • 散热器组件包括散热器(20)和附接在散热器的相对侧上的一对夹子(10),用于将散热器固定到电子部件(40)上。 散热器包括基座(22)和多个翅片(24)。 一对突起(28)形成在相邻的两个翅片的底部上。 因此,在基座,两个相邻的翅片和突起之间形成锁定槽(29)。 该夹子包括一个大致接收在锁定槽中的按压部分(12),一对从按压部分的相对端延伸的延伸部分(14)和一对形成在延伸部分的自由端上的钩(16)。 当夹子变形以使钩与电子部件接合时,夹子的按压部分将散热器朝向电子部件按压。
    • 10. 发明授权
    • Clip for heat sink
    • 夹子为散热片
    • US06318452B1
    • 2001-11-20
    • US09613106
    • 2000-07-10
    • DongYun Lee
    • DongYun Lee
    • H05K720
    • H01L23/4093H01L2924/0002H01L2924/00
    • A clip includes a body (10) having a spring portion (12) and a leg (14) formed on a first end of the spring portion for engaging with a first side of a heat generating device, such as a central processing unit module. A fastener (20) has a spring plate (24) connected to a second end of the spring portion of the body and is engageable with an opposite second side of the heat generating device for securing a heat sink to the heat generating device. A pair of connecting tabs (26) extends from the fastener above the body for pivotally retaining an actuating member (30) therebetween. The actuating member forms cams (34) engaging the spring portion of the body whereby, when the actuating member is manually operated, the camming engagement between the actuating member and the spring portion drives the fastener to engage the second side of the heat generating device.
    • 夹具包括具有弹簧部分(12)的主体(10)和形成在弹簧部分的第一端上的腿部(14),用于与例如中央处理单元模块的发热装置的第一侧接合。 紧固件(20)具有连接到主体的弹簧部分的第二端的弹簧板(24),并且可与发热装置的相对的第二侧接合,用于将散热器固定到发热装置。 一对连接突片(26)从主体上方的紧固件延伸,用于在其间枢转地保持致动构件(30)。 致动构件形成与主体的弹簧部分接合的凸轮(34),由此当致动构件被手动操作时,致动构件和弹簧部分之间的凸轮接合驱动紧固件以接合发热装置的第二侧。