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1. 发明申请

US20130073878A1 APPARATUS AND METHODS FOR AN INTERCONNECT POWER MANAGER 有权
标题翻译：互连电源管理器的装置和方法
公开(公告)号：US20130073878A1
公开(公告)日：2013-03-21
申请号：US13434605
申请日：2012-03-29
申请人： Doddaballapur N. Jayasimha , Drew E. Wingard , Stephen W. Hamilton
发明人： Doddaballapur N. Jayasimha , Drew E. Wingard , Stephen W. Hamilton
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.
摘要翻译：互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

2. 发明授权

US08190804B1 Various methods and apparatus for a memory scheduler with an arbiter 有权
标题翻译：用于具有仲裁器的存储器调度器的各种方法和装置
公开(公告)号：US08190804B1
公开(公告)日：2012-05-29
申请号：US12402707
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard
发明人： Krishnan Srinivasan , Drew E. Wingard
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1615
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器具有流水线仲裁器，以确定哪个请求将访问目标存储器核心。流水线在多于一个时钟周期的时间内在仲裁器内分阶段发生。流水线仲裁器使用两个或更多个加权因素影响并行处理的仲裁决策。存储器调度器中的预测调度器使用来自前一周期的数据在当前时钟周期内作出关于请求的仲裁决定，其中作出仲裁决定以提高在集成电路中服务的请求的整体系统效率。

3. 发明授权

US08032676B2 Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device 有权
标题翻译：用于管理发送设备和接收设备之间的带宽不匹配的方法和设备
公开(公告)号：US08032676B2
公开(公告)日：2011-10-04
申请号：US10980505
申请日：2004-11-02
申请人： Drew E. Wingard , Glenn S. Vinogradov
发明人： Drew E. Wingard , Glenn S. Vinogradov
IPC分类号： G06F3/00 , G06F13/00 , G06F13/40 , G06F11/00
CPC分类号： H04L49/3054 , H04L49/109
摘要： Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.
摘要翻译：描述了用于在通信结构上的系统的功能块之间传送信息的装置，系统和方法的实施例。速率逻辑可以耦合到通信结构。速率逻辑被配置为确定发送设备的第一数据带宽能力与发送设备的第二数据带宽能力之间的数据带宽差异，或2）通信结构的第三数据带宽能力。

4. 发明授权

US07660932B2 Composing on-chip interconnects with configurable interfaces 有权
标题翻译：组合片上互连与可配置接口
公开(公告)号：US07660932B2
公开(公告)日：2010-02-09
申请号：US12022912
申请日：2008-01-30
申请人： Chien Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
发明人： Chien Chun Chou , Wolf-Dietrich Weber , Drew E. Wingard
IPC分类号： G06F13/00
CPC分类号： H04L69/18 , G06F15/7825
摘要： Embodiments of apparatuses, systems, and methods are described for a machine-readable medium having instructions stored thereon, which, when executed by a machine, to cause the machine to generate a representation of an apparatus. The apparatus includes a bridge agent, a first interconnect, and a second interconnect. The bridge agent is configured by bridge control signals to control transmission of a communication between the first interconnect and the second interconnect. The representation may be a sequence of instructions written in a programming language to mimic in a computer simulation environment attributes derived from a projected fabricated hardware instance of the apparatus.
摘要翻译：对于具有存储在其上的指令的机器可读介质描述了装置，系统和方法的实施例，当由机器执行时，该机器可读介质使机器产生装置的表示。该装置包括桥接器，第一互连和第二互连。桥接代理由桥控制信号配置，以控制第一互连和第二互连之间的通信的传输。该表示可以是以编程语言编写的指令序列，以在计算机模拟环境中模仿从该装置的投影制造的硬件实例导出的属性。

5. 发明授权

US07647441B2 Communications system and method with multilevel connection identification 有权
标题翻译：具有多层连接识别的通信系统和方法
公开(公告)号：US07647441B2
公开(公告)日：2010-01-12
申请号：US11881526
申请日：2007-07-26
申请人： Drew E. Wingard , Jay S. Tomlinson
发明人： Drew E. Wingard , Jay S. Tomlinson
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： H04L12/403 , G06F13/385 , G06F13/4243 , H04L12/66
摘要： An embodiment includes a communication medium coupled to a plurality of the functional blocks in an integrated circuit. Three or more of the initiator functional blocks communicate with a target functional block by sending requests having an associated identifier to indicate a transaction stream that the request is part of. At least a first and a second of buffer are associated with the target functional block at an interface of the target functional block to the communication medium and receive requests having the associated identifiers from the three or more initiator functional blocks through a shared common connection point for the interface. The communication medium implements a mapping algorithm to map requests from a first initiator functional block as well as requests from a third initiator functional block to a first dedicated buffer based on the associated identifiers. The mapping algorithm also maps requests from a second initiator functional block to a second buffer based on the associated identifier.
摘要翻译：一个实施例包括耦合到集成电路中的多个功能块的通信介质。三个或更多个发起者功能块通过发送具有关联标识符的请求来与目标功能块通信，以指示该请求是其一部分的事务流。至少第一和第二缓冲器与目标功能块的接口处的通信介质与目标功能块相关联，并且通过共享公共连接点从三个或更多个启动器功能块接收具有相关标识符的请求，界面。通信介质实现映射算法，以基于相关联的标识符来映射来自第一启动器功能块的请求以及来自第三启动器功能块的请求到第一专用缓冲器。映射算法还基于相关联的标识符将来自第二启动器功能块的请求映射到第二缓冲器。

6. 发明申请

US20120117301A1 METHODS AND APPARATUS FOR VIRTUALIZATION IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路虚拟化的方法和设备
公开(公告)号：US20120117301A1
公开(公告)日：2012-05-10
申请号：US13288582
申请日：2011-11-03
申请人： Drew E. Wingard
发明人： Drew E. Wingard
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. A centralized Memory Management logic Unit (MMU) is located in the interconnect for virtualization and sharing of integrated circuit resources including target cores between the one or more initiator IP cores. A master translation look aside buffer (TLB) stores virtualization and sharing information in the entries of the master TLB. A set of two or more translation look aside buffers (TLBs) locally store virtualization and sharing information replicated from the master TLB. Logic in the MMU or other software updates the virtualization and sharing information replicated from the master TLB in the entries of one or more of the set of local TLBs.
摘要翻译：描述了用于在一个或多个发起者IP核与耦合到互连的一个或多个目标IP核之间进行交易的各种方法和装置。集成的内存管理逻辑单元（MMU）位于互连中，用于集成电路资源的虚拟化和共享，包括一个或多个启动器IP内核之间的目标内核。主翻译看缓冲区（TLB）将虚拟化和共享信息存储在主TLB的条目中。一组两个或更多的翻译旁边缓冲区（TLB）本地存储从主TLB复制的虚拟化和共享信息。 MMU或其他软件中的逻辑更新在主TLB中的一个或多个本地TLB的条目中复制的虚拟化和共享信息。

7. 发明申请

US20120036509A1 APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AS WELL AS PER-TAG MEMORY ACCESS SCHEDULING WITHIN A THREAD AND ACROSS TWO OR MORE THREADS 有权
标题翻译：设备和方法一致地执行每个线程，就像在线程和两个或更多的线程中的每个TAG存储器访问调度一样
公开(公告)号：US20120036509A1
公开(公告)日：2012-02-09
申请号：US12852355
申请日：2010-08-06
申请人： KRISHNAN SRINIVASAN , RUBEN KHAZHAKYAN , HARUTYUN ASLANYAN , DREW E. WINGARD , CHIEN-CHUN CHOU
发明人： KRISHNAN SRINIVASAN , RUBEN KHAZHAKYAN , HARUTYUN ASLANYAN , DREW E. WINGARD , CHIEN-CHUN CHOU
IPC分类号： G06F9/46 , G06F12/14 , G06F1/12 , G06F12/00
CPC分类号： G06F9/526 , G06F12/0879 , G06F12/0882
摘要： A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
摘要翻译：集成电路包括启动器知识产权（IP）核心，目标IP核，互连以及标签和线程逻辑的方法，装置和系统。目标IP核可以包括耦合到发起者IP核的存储器。另外，互连可以允许集成电路在一个或多个启动器知识产权（IP）核心和耦合到互连的一个或多个目标IP核之间传送事务。标签和线程逻辑可以被配置为同时执行线程内和跨多个线程的每线程和每标签内存访问调度，使得标签和线程逻辑管理标签和线程以允许每标签和每个线程调度的内存从发起者IP内核访问来自发起者IP核的请求的初始发布顺序的顺序的请求。

8. 发明申请

US20100211935A1 METHOD AND APPARATUS FOR ESTABLISHING A QUALITY OF SERVICE MODEL 有权
标题翻译：建立质量服务模式的方法与装置
公开(公告)号：US20100211935A1
公开(公告)日：2010-08-19
申请号：US12706656
申请日：2010-02-16
申请人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Chien-Chun Chou , Drew E. Wingard
IPC分类号： G06F9/44 , G06F9/46 , G06F12/00
CPC分类号： H04L47/10 , H04L47/2425 , H04L47/70 , H04L47/805 , H04L47/821 , H04L47/827
摘要： In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.
摘要翻译：通常，公开了实现服务质量（QoS）模型的方法和装置。可以满足与发起网络设备的服务质量（QoS）合同。可以在起始网络设备中的第一次小于等于序号到达间隔的时间来接收请求。序号表示一组请求中请求的位置。已经服务的请求可以在小于或等于常数项加上序数与服务间隔倍数的第二时间返回给启动器。

9. 发明申请

US20100057400A1 METHOD AND SYSTEM TO MONITOR, DEBUG, AND ANALYZE PERFORMANCE OF AN ELECTRONIC DESIGN 有权
标题翻译：监测，调试和分析电子设计性能的方法和系统
公开(公告)号：US20100057400A1
公开(公告)日：2010-03-04
申请号：US12204156
申请日：2008-09-04
申请人： Chien-Chun Chou , Stephen W. Hamilton , Drew E. Wingard , Pascal Chauvet
发明人： Chien-Chun Chou , Stephen W. Hamilton , Drew E. Wingard , Pascal Chauvet
IPC分类号： G21C17/00
CPC分类号： G06F11/3466 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.
摘要翻译：描述了提供电子设计的仪器和分析的各种方法和装置。性能监视装置可以位于所制造的集成电路的互连上。事件测量模块（EM）包括一个事件发生器子模块，该事件发生器子模块通过互连产生与发起者知识产权（IP）核心和目标IP内核之间的事务相关联的监视事件和事件测量。 EM还包括软件可见寄存器块，其提供用于控制EM监视的一个或多个事务的软件访问以及配置与该事务相关联的一个或多个参数以进行跟踪。 EM还包括一个过滤子模块，该过滤子模块根据从软件接收的信息来选择要监视的事务。性能计数器模块将从EM接收到的事件和事件测量聚合到与互连上的IP内核之间的事务相关联的性能度量数量。

10. 发明申请

US20090235020A1 VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING 有权
标题翻译：各种方法和地址倾斜装置
公开(公告)号：US20090235020A1
公开(公告)日：2009-09-17
申请号：US12402704
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
IPC分类号： G06F12/06 , G06F13/28
CPC分类号： G06F12/0607
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器耦合到包括一组存储器的目标存储器核心。存储器调度器包含两个或多个可配置的地址拼接功能，用于将请求中请求的数据的输入地址变换到目标存储器核，以确定存储器组中的哪些物理地址将用于第一请求。两个或多个可配置的地址拼接功能可由用户编程，以在目标存储器核心中创建两个或更多明显不同的存储器区域。每个存储器区域都有自己的不同的平铺功能，基于用户选择的配置参数1）和2）存储在存储器调度器中的平铺寄存器中。多个拼接功能被配置为在集成电路中同时运行。

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