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1. 发明授权

US08895352B2 Method to improve nucleation of materials on graphene and carbon nanotubes 有权
标题翻译：改善石墨烯和碳纳米管材料成核的方法
公开(公告)号：US08895352B2
公开(公告)日：2014-11-25
申请号：US12476676
申请日：2009-06-02
申请人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
发明人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
IPC分类号： H01L51/40 , H01L21/02 , H01L29/66 , H01L29/786
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.
摘要翻译：提供了在碳基材料上形成材料的薄涂层的技术。一方面，提供了在碳系材料的表面上形成薄涂层的方法。该方法包括以下步骤。在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。

2. 发明授权

US08816333B2 Method to improve nucleation of materials on graphene and carbon nanotubes 有权
公开(公告)号：US08816333B2
公开(公告)日：2014-08-26
申请号：US13482262
申请日：2012-05-29
申请人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
发明人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
IPC分类号： H01L51/00
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

3. 发明申请

US20070161214A1 High k gate stack on III-V compound semiconductors 审中-公开
标题翻译： III-V复合半导体上的高k栅极叠层
公开(公告)号：US20070161214A1
公开(公告)日：2007-07-12
申请号：US11327675
申请日：2006-01-06
申请人： Jean Fompeyrine , Edward Kiewra , Steven Koester , Devendra Sadana , David Webb
发明人： Jean Fompeyrine , Edward Kiewra , Steven Koester , Devendra Sadana , David Webb
IPC分类号： H01L21/20 , H01L23/58
CPC分类号： H01L21/3205 , H01L21/02148 , H01L21/02181 , H01L21/02271 , H01L21/28158 , H01L21/3145 , H01L21/31645 , H01L21/32051 , H01L29/513 , H01L29/518 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.
摘要翻译：提供了在III-V族化合物半导体的这种GaAs的表面上形成高k栅极叠层（介电常数大于二氧化硅的介电常数）的方法。该方法包括使III-V族化合物半导体材料进行从III-V族化合物半导体材料的表面除去天然氧化物的预清洗工艺; 在III-V族化合物半导体材料的清洁表面上原位形成半导体，例如非晶Si层; 以及在所述半导体层上形成介电常数大于二氧化硅的电介质材料。在一些实施例中，在形成电介质材料之前，半导体层被部分地或完全地转换成包括至少包括AO x N y Y y的表面层的层。根据本发明，A是半导体材料，优选Si，x为0至1，y为0至1，x和y都不为零。

4. 发明申请

US20070158851A1 Method to Improve Time Dependent Dielectric Breakdown 失效
标题翻译：改善时间依赖介质破坏的方法
公开(公告)号：US20070158851A1
公开(公告)日：2007-07-12
申请号：US11306825
申请日：2006-01-12
申请人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Vincent McGahay , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Vincent McGahay , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.
摘要翻译：在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

5. 发明申请

US20050287718A1 INTEGRATED SOI FINGERED DECOUPLING CAPACITOR 有权
标题翻译：集成的SOI手指解除电容器
公开(公告)号：US20050287718A1
公开(公告)日：2005-12-29
申请号：US10710256
申请日：2004-06-29
申请人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： H01L21/00 , H01L21/334 , H01L21/336 , H01L21/8242 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.
摘要翻译：本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物，具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

6. 发明申请

US20070267386A1 POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY 有权
标题翻译：后期化学机械抛光蚀刻改进时间依赖介质断开可靠性
公开(公告)号：US20070267386A1
公开(公告)日：2007-11-22
申请号：US11833283
申请日：2007-08-03
申请人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James Demarest , Ronald Filippi , Roy Iggulden , Edward Kiewra , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

7. 发明申请

US20060097394A1 DETECTION OF RESIDUAL LINER MATERIALS AFTER POLISHING IN DAMASCENE PROCESS 失效
标题翻译：在破碎过程中抛光后残留衬里材料的检测
公开(公告)号：US20060097394A1
公开(公告)日：2006-05-11
申请号：US10904329
申请日：2004-11-04
申请人： Ronald Filippi , Roy Iggulden , Edward Kiewra , Stephen Loh , Ping-Chuan Wang
发明人： Ronald Filippi , Roy Iggulden , Edward Kiewra , Stephen Loh , Ping-Chuan Wang
IPC分类号： H01L23/52
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/7688 , H01L22/24 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
摘要翻译：用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。此外，标记层包括与电介质层分离的层。另外，紫外线可检测材料包括荧光材料或磷光材料。

8. 发明申请

US20050275054A1 Autonomic thermal monitor and controller for thin film devices 失效
标题翻译：用于薄膜器件的自动热监测器和控制器
公开(公告)号：US20050275054A1
公开(公告)日：2005-12-15
申请号：US10853800
申请日：2004-05-25
申请人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zachary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： G01K7/01 , H01L27/02 , H01L29/66 , H01L31/0392
CPC分类号： H01L27/0248 , G01K7/01 , H01L29/66992
摘要： A thermal monitor diode is provided that comprises a silicon thin film on an insulator mounted on a silicon substrate. An opening extends through the silicon thin film and through the insulator and partially into the silicon substrate and terminates at an end wall. A conductive material is disposed in the opening and extends to the end wall. The substrate has a P/N junction formed therein adjacent the end wall, and an insulating spacer material surrounds the conductive material and is sufficiently thin to allow temperature excursions in the silicon thin film to pass therethrough. The invention also contemplates a method of forming the diode.
摘要翻译：提供一种热监测二极管，其包括安装在硅衬底上的绝缘体上的硅薄膜。开口延伸穿过硅薄膜并穿过绝缘体并部分地延伸到硅衬底中并终止于端壁。导电材料设置在开口中并延伸到端壁。衬底具有邻近端壁形成的P / N结，并且绝缘间隔物材料围绕导电材料并且足够薄以允许硅薄膜中的温度偏移通过。本发明还考虑了形成二极管的方法。

9. 发明申请

US20120326265A1 METHOD OF FORMING MEMORY CELL ACCESS DEVICE 有权
标题翻译：形成记忆细胞存取装置的方法
公开(公告)号：US20120326265A1
公开(公告)日：2012-12-27
申请号：US13168753
申请日：2011-06-24
申请人： Erh-Kun Lai , Hsiang-Lan Lung , Edward Kiewra
发明人： Erh-Kun Lai , Hsiang-Lan Lung , Edward Kiewra
IPC分类号： H01L21/762 , H01L27/08 , B82Y99/00
CPC分类号： H01L27/1021 , H01L27/101
摘要： A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.
摘要翻译：存储器件包括一个存取器件，它包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域。第一掺杂半导体区域和第二掺杂半导体区域均形成在单晶半导体本体中，并且在它们之间限定p-n结。第一和第二掺杂半导体区域被实现在形成在单晶半导体本体中的隔离的平行脊中。每个山脊都是锯齿状的，扇形界定半岛; 第一掺杂半导体区域占据岛的下部和脊的上部，并且第二掺杂半导体区占据岛的上部，从而在岛内限定p-n结。

10. 发明申请

US20120235119A1 Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes 有权
标题翻译：改善石墨烯和碳纳米管材料成核的方法
公开(公告)号：US20120235119A1
公开(公告)日：2012-09-20
申请号：US13482262
申请日：2012-05-29
申请人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
发明人： Katherina Babich , Alessandro Callegari , Zhihong Chen , Edward Kiewra , Yanning Sun
IPC分类号： H01L29/775 , H01L29/04
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.
摘要翻译：提供了在碳基材料上形成材料的薄涂层的技术。一方面，提供了在碳系材料的表面上形成薄涂层的方法。该方法包括以下步骤。在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。

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