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1. 发明授权

US07362859B1 Enhancement of utilization of encryption engine 有权
标题翻译：增强加密引擎的利用率
公开(公告)号：US07362859B1
公开(公告)日：2008-04-22
申请号：US09970912
申请日：2001-10-04
申请人： Robert J. Robertson , Edward L. Witzke
发明人： Robert J. Robertson , Edward L. Witzke
IPC分类号： H04K1/04 , H04K1/00
CPC分类号： H04L9/0637 , H04L2209/125
摘要： A method of enhancing throughput of a pipelined encryption/decryption engine for an encryption/decryption process has a predetermined number of stages and provides feedback around the stages (and of such an encryption/decryption engine) by receiving a source datablock for a given stage and encryption/decryption context identifier; indexing according to the encryption/decryption context identifier into a bank of initial variables to retrieve an initial variable for the source datablock; and generating an output datablock from the source datablock and its corresponding initial variable.
摘要翻译：增强用于加密/解密处理的流水线加密/解密引擎的吞吐量的方法具有预定数量的级，并且通过接收给定阶段的源数据块并且在阶段（和这样的加密/解密引擎）周围提供反馈，加密/解密上下文标识符; 根据加密/解密上下文标识符索引到一组初始变量中以检索源数据块的初始变量; 并从源数据块及其对应的初始变量生成输出数据块。

2. 发明授权

US07257093B1 Localized radio frequency communication using asynchronous transfer mode protocol 失效
标题翻译：使用异步传输模式协议的本地化射频通信
公开(公告)号：US07257093B1
公开(公告)日：2007-08-14
申请号：US09975271
申请日：2001-10-10
申请人： Edward L. Witzke , Perry J. Robertson , Lyndon G. Pierson
发明人： Edward L. Witzke , Perry J. Robertson , Lyndon G. Pierson
IPC分类号： H04B7/00
CPC分类号： G06F13/4045 , H04L12/5601 , H04L2012/5607 , H05K1/14 , H05K2201/10098
摘要： A localized wireless communication system for communication between a plurality of circuit boards, and between electronic components on the circuit boards. Transceivers are located on each circuit board and electronic component. The transceivers communicate with one another over spread spectrum radio frequencies. An asynchronous transfer mode protocol controls communication flow with asynchronous transfer mode switches located on the circuit boards.
摘要翻译：一种本地化的无线通信系统，用于在多个电路板之间以及电路板上的电子部件之间进行通信。收发器位于每个电路板和电子元件上。收发器通过扩频无线电频率彼此通信。异步传输模式协议通过位于电路板上的异步传输模式开关控制通信流。

3. 发明授权

US06560727B1 Bit error rate tester using fast parallel generation of linear recurring sequences 有权
标题翻译：误码率测试仪使用快速并行生成线性重复序列
公开(公告)号：US06560727B1
公开(公告)日：2003-05-06
申请号：US09426073
申请日：1999-10-21
申请人： Lyndon G. Pierson , Edward L. Witzke , Joseph H. Maestas
发明人： Lyndon G. Pierson , Edward L. Witzke , Joseph H. Maestas
IPC分类号： G06F1100
CPC分类号： G01R31/3171 , G01R31/319
摘要： A fast method for generating linear recurring sequences by parallel linear recurring sequence generators (LRSGs) with a feedback circuit optimized to balance minimum propagation delay against maximal sequence period. Parallel generation of linear recurring sequences requires decimating the sequence (creating small contiguous sections of the sequence in each LRSG). A companion matrix form is selected depending on whether the LFSR is right-shifting or left-shifting. The companion matrix is completed by selecting a primitive irreducible polynomial with 1's most closely grouped in a corner of the companion matrix. A decimation matrix is created by raising the companion matrix to the (n*k)th power, where k is the number of parallel LRSGs and n is the number of bits to be generated at a time by each LRSG. Companion matrices with 1's closely grouped in a corner will yield sparse decimation matrices. A feedback circuit comprised of XOR logic gates implements the decimation matrix in hardware. Sparse decimation matrices can be implemented with minimum number of XOR gates, and therefore a minimum propagation delay through the feedback circuit. The LRSG of the invention is particularly well suited to use as a bit error rate tester on high speed communication lines because it permits the receiver to synchronize to the transmitted pattern within 2n bits.
摘要翻译：一种通过并行线性循环序列发生器（LRSG）生成线性重复序列的快速方法，其具有优化的平衡最小传播延迟与最大序列周期的反馈电路。线性重复序列的并行生成需要抽取序列（在每个LRSG中创建序列的小连续部分）。根据LFSR是右移还是左移，选择伴随矩阵形式。通过选择在伴随矩阵的角落中最紧密分组的1的原始不可约多项式来完成伴随矩阵。通过将伴随矩阵提高到（n * k）个功率来产生抽取矩阵，其中k是并行LRSG的数量，n是每个LRSG一次生成的比特数。具有1个紧密组合在一个角落中的伴随矩阵将产生稀疏抽取矩阵。由XOR逻辑门组成的反馈电路以硬件实现抽取矩阵。稀疏抽取矩阵可以用最小数量的异或门实现，因此可以通过反馈电路实现最小的传播延迟。本发明的LRSG特别适用于在高速通信线路上用作误码率测试仪，因为它允许接收机在2n位内与发射模式同步。

4. 发明授权

US08914648B1 Stateless and stateful implementations of faithful execution 有权
标题翻译：无状态和有状态地执行忠实执行
公开(公告)号：US08914648B1
公开(公告)日：2014-12-16
申请号：US12542072
申请日：2009-08-17
申请人： Lyndon G. Pierson , Edward L. Witzke , Thomas D. Tarman , Perry J. Robertson , John M. Eldridge , Philip L. Campbell
发明人： Lyndon G. Pierson , Edward L. Witzke , Thomas D. Tarman , Perry J. Robertson , John M. Eldridge , Philip L. Campbell
IPC分类号： G06F11/30
CPC分类号： G06F21/52 , G06F21/64 , H04L9/0656 , H04L9/32
摘要： A faithful execution system includes system memory, a target processor, and protection engine. The system memory stores a ciphertext including value fields and integrity fields. The value fields each include an encrypted executable instruction and the integrity fields each include an encrypted integrity value for determining whether a corresponding one of the value fields has been modified. The target processor executes plaintext instructions decoded from the ciphertext while the protection engine is coupled between the system memory and the target processor. The protection engine includes logic to retrieve the ciphertext from the system memory, decrypt the value fields into the plaintext instructions, perform an integrity check based on the integrity fields to determine whether any of the corresponding value fields have been modified, and provide the plaintext instructions to the target processor for execution.
摘要翻译：忠实的执行系统包括系统内存，目标处理器和保护引擎。系统存储器存储包括值字段和完整性字段的密文。值字段各自包括加密的可执行指令，并且完整性字段各自包括加密的完整性值，用于确定值字段中对应的一个值是否已被修改。当保护引擎耦合在系统存储器和目标处理器之间时，目标处理器执行从密文解码的明文指令。保护引擎包括从系统存储器检索密文的逻辑，将值字段解密为明文指令，根据完整性字段执行完整性检查，以确定是否已对任何相应的值字段进行了修改，并提供明文指令到目标处理器执行。

5. 发明授权

US06209077B1 General purpose programmable accelerator board 有权
标题翻译：通用可编程加速板
公开(公告)号：US06209077B1
公开(公告)日：2001-03-27
申请号：US09217099
申请日：1998-12-21
申请人： Perry J. Robertson , Edward L. Witzke
发明人： Perry J. Robertson , Edward L. Witzke
IPC分类号： G06F928
CPC分类号： G06F15/7867 , G06F9/3879
摘要： A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.
摘要翻译：一种通用加速器板和加速方法，包括使用：一个或多个可编程逻辑器件; 多个存储块; 总线接口，用于在存储器块和板外部的设备之间传送数据; 以及用于向可编程逻辑器件提供对存储器块中的数据执行逻辑的动态编程能力。

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