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1. 发明申请

US20180164370A1 GENERIC WIDTH INDEPENDENT PARALLEL CHECKER FOR A DEVICE UNDER TEST 审中-公开
公开(公告)号：US20180164370A1
公开(公告)日：2018-06-14
申请号：US15375542
申请日：2016-12-12
申请人： STMicroelectronics International N.V.
发明人： Tejinder Kumar , Suchi Prabhu Tandel , Rakesh Malik
IPC分类号： G01R31/317 , G01R31/3193
CPC分类号： G01R31/31703 , G01R31/3171 , G01R31/31932 , G01R31/31935 , G11C15/00 , G11C29/36 , G11C29/38 , G11C29/44 , G11C2029/0405 , G11C2029/2602
摘要： Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

2. 发明授权

US09778678B2 Method and apparatus for clocked data eye measurement 有权
公开(公告)号：US09778678B2
公开(公告)日：2017-10-03
申请号：US14830138
申请日：2015-08-19
申请人： International Business Machines Corporation
发明人： Layne A. Berge , Benjamin A. Fox , Wesley D. Martin , George R. Zettles, IV
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G01R31/3171 , H04L1/20
摘要： Method and apparatus for clocked data eye measurement at synchronous interfaces is provided. A receiver may generate first vector information corresponding to data received on at least one communication channel at the receiver. The receiver may generate second information regarding when the data was latched by a clock signal, the clock signal being received on a separate communication channel at the receiver. The first vector information may be combined with the second information to generate combined information, the combined information indicating a quality of latching the data.

3. 发明授权

US09633698B2 Dynamic control of signaling power based on an error rate 有权
公开(公告)号：US09633698B2
公开(公告)日：2017-04-25
申请号：US14280313
申请日：2014-05-16
申请人： QUALCOMM Incorporated
发明人： Dexter Tamio Chun , Vaishnav Srinivas , David Ian West , Deepti Vijayalakshmi Sriramagiri , Jungwon Suh , Jason Thurston
IPC分类号： G06F11/00 , G11C5/14 , G06F11/07 , G06F11/10 , G01R31/317
CPC分类号： G11C5/147 , G01R31/31709 , G01R31/3171 , G06F11/076 , G06F11/1004
摘要： Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

4. 发明授权

US09435840B2 Determining worst-case bit patterns based upon data-dependent jitter 有权
标题翻译：根据数据相关抖动确定最差情况下的位模式
公开(公告)号：US09435840B2
公开(公告)日：2016-09-06
申请号：US14149806
申请日：2014-01-07
申请人： Mentor Graphics Corporation
发明人： Vladimir Dmitriev-Zdorov
IPC分类号： G06F11/07 , G01R31/00 , H04L1/00 , G06F11/36 , G01R31/317
CPC分类号： G01R31/00 , G01R31/31709 , G01R31/3171 , H04L1/00 , H04L1/203 , H04L1/205
摘要： The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.
摘要翻译：专利申请公开了针对给定的信道步或边缘响应，比特间隔和数据相关抖动表可以考虑到数据相关抖动的影响，通过构建最坏情况模式来直接确定最小眼或位错误率开放的机制。这些机制可以基于构建一个索引的抖动样本表，准备一个与抖动样本相对应的连接元素形式的结构，然后应用动态规划来确定连通元素的路径。

5. 发明申请

US20160110237A1 METHOD TO DETERMINE BER (BIT ERROR RATE) FROM AN EYE DIAGRAM 有权
标题翻译：从眼图中确定误码率（误码率）的方法
公开(公告)号：US20160110237A1
公开(公告)日：2016-04-21
申请号：US14519703
申请日：2014-10-21
申请人： Tektronix, Inc.
发明人： Richard J. Poulo
IPC分类号： G06F11/07
CPC分类号： G06F11/076 , G01R13/029 , G01R31/3171
摘要： A system and method for calculating a bit error rate for a mask is described. For each time during the time duration of the mask, the minimum and maximum voltages of the mask at that time are determined. The maximum bit error rate can be calculated for each time by integrating between those voltages. The maximum bit error rate for all times during the time duration of the mask can be selected as the maximum bit error rate for the mask.
摘要翻译：描述用于计算掩码的误码率的系统和方法。对于掩模的持续时间期间的每一次，确定该时刻的掩模的最小和最大电压。通过在这些电压之间进行积分，可以每次计算出最大误码率。掩模持续时间内的所有时间的最大误码率可以被选择为掩码的最大误码率。

6. 发明授权

US09015537B2 Bit error rate based wear leveling for solid state drive memory 有权
标题翻译：固态硬盘存储器的基于误码率的磨损均衡
公开(公告)号：US09015537B2
公开(公告)日：2015-04-21
申请号：US14101655
申请日：2013-12-10
申请人： International Business Machines Corporation
发明人： Thomas J. Griffin , Dustin J. Vanstee
IPC分类号： G06F11/00 , G11C29/00 , G01R31/28 , H03M13/00 , G01R31/317 , G06F11/10 , G11C16/34 , G06F11/07 , G06F11/16 , G11C11/406 , G11C16/10 , G11C16/14 , G11C16/16 , G11C29/42 , G11C29/50 , H04L1/20
CPC分类号： G01R31/3171 , G06F11/008 , G06F11/076 , G06F11/1048 , G06F11/1068 , G06F11/16 , G11C11/406 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468 , G11C16/3495 , G11C29/42 , G11C29/50 , H04L1/203
摘要： According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
摘要翻译：根据示例性实施例，提供了一种用于固态驱动器（SSD）中的基于误码率（BER）的磨损均衡的系统。确定SSD中的块的块级BER值。块的调整PE周期计数根据块级BER值递增或递减。然后根据调整后的PE循环次数在SSD中进行磨损均衡。

7. 发明授权

US08972806B2 Self-test design for serializer / deserializer testing 有权
标题翻译：串行器/解串器测试的自检设计
公开(公告)号：US08972806B2
公开(公告)日：2015-03-03
申请号：US13654833
申请日：2012-10-18
申请人： Applied Micro Circuits Corporation
发明人： Glen Miller
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/3171 , G01R31/31715
摘要： Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.
摘要翻译：本文描述了对集成芯片的数字排序组件的测试。作为示例，为具有不同序列生成（例如，传输）和序列监视（例如，接收）频率的单向集成芯片提供自检程序。可以将测试逻辑组件添加到集成芯片以将序列产生频率与序列监视频率相匹配。这可以通过修改在第二数据位可接收的第一数据位上产生的序列，以及将经修改的序列引导到被配置为在第二数据位上操作的集成芯片的序列监视组件，从而促进单向序列生成组件的自检。

8. 发明申请

US20140372813A1 METHOD FOR VERIFYING BAD PATTERN IN TIME SERIES SENSING DATA AND APPARATUS THEREOF 有权
标题翻译：时间序列传感数据验证方法的方法及装置
公开(公告)号：US20140372813A1
公开(公告)日：2014-12-18
申请号：US14306967
申请日：2014-06-17
申请人： SAMSUNG SDS CO., LTD.
发明人： Kae Young SHIN , Dae Jung AHN , Dae Hong SEO , Woo Young JUNG
IPC分类号： G06F11/07
CPC分类号： G06F11/0736 , G01R31/3171 , G06F11/0703 , G06F11/0706 , G06F11/076 , G06F11/0772 , G06F11/079 , H03M13/015
摘要： A method for verifying bad pattern in time series sensing data by calculating a bad pattern error rate, which can be applied to the time series sensing data measured and produced from a predetermined sensor provided in predetermined equipment, and an apparatus thereof are provided. The method includes receiving information on the bad pattern applied to time series sensing data measured by a suspicious sensor, accessing the time series sensing data of each product, generated by the suspicious sensor during a verification period, calculating similarity measures between the bad pattern based on the bad pattern information and the time series sensing data for each product, and calculating an error rate of the bad pattern based on the similarity measures.
摘要翻译：提供了一种用于通过计算可以应用于从预定设备中提供的预定传感器测量和产生的时间序列感测数据的错误模式错误率来验证时间序列感测数据中的不良图案的方法及其装置。该方法包括接收关于由可疑传感器测量的时间序列感测数据的不良图案的信息，在验证期间访问由可疑传感器产生的每个产品的时间序列感测数据，计算基于每个产品的不良图案信息和时间序列感测数据，并且基于相似度测量来计算不良图案的错误率。

9. 发明申请

US20140281716A1 ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF 有权
标题翻译：模拟块和测试块用于测试
公开(公告)号：US20140281716A1
公开(公告)日：2014-09-18
申请号：US13802223
申请日：2013-03-13
申请人： Xilinx, Inc.
发明人： Sarosh I. Azad
IPC分类号： G06F11/27
CPC分类号： G06F11/27 , G01R31/3167 , G01R31/3171 , G01R31/31716
摘要： An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.
摘要翻译：公开了一种通常涉及片上系统的装置。在该装置中，片上系统具有至少一个模拟块，输入/输出接口，数据测试块和处理单元。处理单元耦合到输入/输出接口以控制对至少一个模拟块的访问。数据测试块通过输入/输出接口耦合到至少一个模拟块。处理单元耦合到数据测试块并且被配置为执行具有至少一个测试图案的测试代码。在由处理单元执行的测试代码的控制下的数据测试块被配置为用测试图案测试至少一个模拟块。

10. 发明申请

US20140258796A1 DETERMINATION OF OPTIMUM THRESHOLD VOLTAGE TO READ DATA VALUES IN MEMORY CELLS 有权
标题翻译：确定最佳阈值电压以读取存储器单元中的数据值
公开(公告)号：US20140258796A1
公开(公告)日：2014-09-11
申请号：US13794716
申请日：2013-03-11
申请人： SEAGATE TECHNOLOGY LLC
发明人： Mai A. Ghaly , Bruce Douglas Emo
IPC分类号： H03M13/15
CPC分类号： G06F11/1008 , G01R31/3171 , G06F11/1048 , G11C7/14 , G11C16/3404 , G11C29/021 , G11C29/028
摘要： An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about the initial value sufficient to fit a polynomial curve. A minimum is used to determine the lowest bit error rate and corresponding optimum threshold voltage. This voltage is adopted as the new threshold voltage for reading the given data.
摘要翻译：自适应搜索方案导致阈值电压与初始值相比具有较低的误码率。使用初始参考电压，并且测量关于初始值的电压的设定步长的数据，以足以拟合多项式曲线。最小值用于确定最低误码率和相应的最佳阈值电压。该电压被用作读取给定数据的新阈值电压。

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