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1. 发明授权

US08768994B2 Filter auto-calibration using multi-clock generator 有权
标题翻译：使用多时钟发生器滤波自动校准
公开(公告)号：US08768994B2
公开(公告)日：2014-07-01
申请号：US12910232
申请日：2010-10-22
申请人： Feng Wei Kuo , Mei-Show Chen , Chewn-Pu Jou , Ying-Ta Lu , Jia-Liang Chen
发明人： Feng Wei Kuo , Mei-Show Chen , Chewn-Pu Jou , Ying-Ta Lu , Jia-Liang Chen
IPC分类号： G06F17/10 , H04N5/50 , H04L27/06 , H04B1/18
CPC分类号： H03H21/0067 , H03D3/007 , H03H2021/0081 , H03H2210/04 , H03J2200/08 , H03L7/07 , H03L7/0816 , H03L7/087 , H03L7/193 , H03L7/1976 , H04B1/30
摘要： A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.
摘要翻译：滤波器自动校准系统包括多时钟模块。多时钟模块包括多时钟发生器，其被配置为基于通道设置产生具有可变频率的时钟信号。至少有一个要校准的过滤器。自动校准控制模块被配置为基于通道设置来控制至少一个滤波器的校准。多时钟模块被配置为将可变频率时钟信号提供给至少一个滤波器和自动校准控制模块，并且至少一个滤波器耦合到自动校准控制模块。

2. 发明授权

US08547151B2 Phase-locked loops that share a loop filter 有权
标题翻译：共享环路滤波器的锁相环路
公开(公告)号：US08547151B2
公开(公告)日：2013-10-01
申请号：US13407394
申请日：2012-02-28
申请人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/06 , H03L7/093 , H03L7/099
摘要： A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.
摘要翻译：集成电路的管芯堆叠包括多个管芯。芯片堆叠中的每个裸片包括锁相环（PLL）。每个模具中的PLL共享一个环路滤波器和其他相应的电路。

3. 发明申请

US20130120035A1 LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP 有权
标题翻译：锁定检测器和检测锁相状态的方法
公开(公告)号：US20130120035A1
公开(公告)日：2013-05-16
申请号：US13297658
申请日：2011-11-16
申请人： Feng Wei KUO , Kyle YEN , Huan-Neng CHEN , Yen-Jen CHEN , Chewn-Pu JOU
发明人： Feng Wei KUO , Kyle YEN , Huan-Neng CHEN , Yen-Jen CHEN , Chewn-Pu JOU
IPC分类号： H03L7/08
CPC分类号： H03L7/095
摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
摘要翻译：用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

4. 发明申请

US20120303688A1 Fast Filter Calibration Apparatus 有权
标题翻译：快速过滤器校准装置
公开(公告)号：US20120303688A1
公开(公告)日：2012-11-29
申请号：US13114788
申请日：2011-05-24
申请人： Feng Wei Kuo
发明人： Feng Wei Kuo
IPC分类号： G06F17/10 , G06J1/00
CPC分类号： H03J1/0008 , H03J2200/03
摘要： A fast filter calibration system comprises a multi clock generator, an analog filter comprising a variable capacitor and a fast calibration apparatus. The fast calibration apparatus further comprises a phase comparator, a frequency detector and a fast calibration unit. The fast calibration unit stores a binary code corresponding to a bandwidth frequency of a filter and initiates a fast filter calibration by calibrating the filter from a binary code close to a guaranteed-by-design binary code for the bandwidth frequency to be calibrated.
摘要翻译：快速滤波器校准系统包括多时钟发生器，包括可变电容器的模拟滤波器和快速校准装置。快速校准装置还包括相位比较器，频率检测器和快速校准单元。快速校准单元存储对应于滤波器的带宽频率的二进制码，并且通过从接近要校准的带宽频率的设计保证的二进制码的二进制码校准滤波器来启动快速滤波器校准。

5. 发明申请

US20140001609A1 INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES 审中-公开
标题翻译：具有噪声抑制特征的插座和半导体封装
公开(公告)号：US20140001609A1
公开(公告)日：2014-01-02
申请号：US14018634
申请日：2013-09-05
申请人： Feng-Wei KUO , Hui Yu LEE , Huan-Neng CHEN , Yen-Jen CHEN , Yu-Ling LIN , Chewn-Pu JOU
发明人： Feng-Wei KUO , Hui Yu LEE , Huan-Neng CHEN , Yen-Jen CHEN , Yu-Ling LIN , Chewn-Pu JOU
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/642 , H01L23/66 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0655 , H01L2223/6677 , H01L2224/131 , H01L2224/14135 , H01L2224/16225 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/19042 , H01L2924/19104 , H01L2924/014
摘要： Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
摘要翻译：插入器和半导体封装实施例提供了隔离和抑制电子噪声，例如半导体封装中的EM发射。插入器包括各种实施例中的屏蔽结构，屏蔽结构阻挡来自噪声源的电噪声与其它电信号或装置。在其他实施例中，屏蔽件包括固体结构和一些实施例以及去耦电容器。耦合结构包括多个包含在条中的焊球，其耦合部件并围绕并包含电噪声源。

6. 发明授权

US08476972B2 Method and apparatus for amplifying a time difference 有权
标题翻译：用于放大时差的方法和装置
公开(公告)号：US08476972B2
公开(公告)日：2013-07-02
申请号：US12813620
申请日：2010-06-11
申请人： You-Jen Wang , Shen-Iuan Liu , Feng Wei Kuo , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： You-Jen Wang , Shen-Iuan Liu , Feng Wei Kuo , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： G06G7/12 , G06G7/26
CPC分类号： G04F10/005
摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.
摘要翻译：时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。每个反相器包括第一NMOS晶体管和第一PMOS晶体管。第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

7. 发明授权

US08314652B2 System and method for RC calibration using phase and frequency 有权
标题翻译：使用相位和频率进行RC校准的系统和方法
公开(公告)号：US08314652B2
公开(公告)日：2012-11-20
申请号：US12777293
申请日：2010-05-11
申请人： Feng Wei Kuo , Tsung-Hsien Tsai , Jia-Liang Chen
发明人： Feng Wei Kuo , Tsung-Hsien Tsai , Jia-Liang Chen
IPC分类号： H03B1/00
CPC分类号： H03H11/12
摘要： An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter.
摘要翻译：通过用截止频率初始化滤波器，将RC滤波器校准为所需的截止频率。输入信号由RC滤波器滤波，以提供具有相位和频率值的滤波器输出信号。如果相位和频率值不满足预定条件，则根据滤波器输出信号的相位和频率值来调整RC滤波器的截止频率。重复滤波和调整直到滤波器输出信号的相位和频率值满足预定条件。校准装置具有频率发生器，电阻 - 电容（RC）滤波器，相位比较器，频率检测器和状态机。相位比较器，频率检测器和状态机被配置为基于RC滤波器的滤波器输出信号将RC滤波器校准到由参考信号指定的截止频率。

8. 发明申请

US20120056769A1 METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS 有权
标题翻译：使用校准和校正灯进行数字转换的方法和系统
公开(公告)号：US20120056769A1
公开(公告)日：2012-03-08
申请号：US12874462
申请日：2010-09-02
申请人： You-Jen WANG , Shen-Iuan LIU , Feng Wei KUO , Chewn-Pu JOU , Fu-Lung HSUEH
发明人： You-Jen WANG , Shen-Iuan LIU , Feng Wei KUO , Chewn-Pu JOU , Fu-Lung HSUEH
IPC分类号： H03M1/50
CPC分类号： G04F10/005
摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.
摘要翻译：公开了时间到数字转换（TDC）的方法和装置。定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

9. 发明申请

US20110304372A1 METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE 有权
标题翻译：用于放大时间差异的方法和装置
公开(公告)号：US20110304372A1
公开(公告)日：2011-12-15
申请号：US12813620
申请日：2010-06-11
申请人： You-Jen WANG , Shen-Iuan LIU , Feng Wei KUO , Chewn-Pu JOU , Fu-Lung HSUEH
发明人： You-Jen WANG , Shen-Iuan LIU , Feng Wei KUO , Chewn-Pu JOU , Fu-Lung HSUEH
IPC分类号： H03H11/26
CPC分类号： G04F10/005
摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.
摘要翻译：时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。每个反相器包括第一NMOS晶体管和第一PMOS晶体管。第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

10. 发明授权

US09275923B2 Band pass filter for 2.5D/3D integrated circuit applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US09275923B2
公开(公告)日：2016-03-01
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56 , H01L23/31 , H01L23/64 , H01L23/66 , H01L25/16 , H01L23/00
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.
摘要翻译：一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。集成无源器件芯片和收发器芯片也布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。

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