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1. 发明授权

US09275923B2 Band pass filter for 2.5D/3D integrated circuit applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US09275923B2
公开(公告)日：2016-03-01
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56 , H01L23/31 , H01L23/64 , H01L23/66 , H01L25/16 , H01L23/00
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.
摘要翻译：一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。集成无源器件芯片和收发器芯片也布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。

2. 发明授权

US09177715B2 System and method for inductive wireless signaling 有权
标题翻译：感应式无线信令系统和方法
公开(公告)号：US09177715B2
公开(公告)日：2015-11-03
申请号：US12952429
申请日：2010-11-23
申请人： Jun-De Jin , Fan-Ming Kuo , Huan-Neng Chen , Ming Hsien Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh
发明人： Jun-De Jin , Fan-Ming Kuo , Huan-Neng Chen , Ming Hsien Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh
IPC分类号： H01F5/00 , H01F38/14 , H01F17/00
CPC分类号： H02J5/005 , H01F5/00 , H01F17/0006 , H01F38/14 , H01F2017/0086 , H02J17/00 , H02J50/12
摘要： A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.
摘要翻译：变压器包括第一和第二半导体衬底。第一半导体衬底包括第一电路，提供第一阻抗的第一线圈和与第一线圈并联耦合的第一电容器。第二半导体衬底包括第二电路，提供第二阻抗并与第一线圈感应耦合的第二线圈以及与第二线圈并联耦合的第二电容器。

3. 发明授权

US09086452B2 Three-dimensional integrated circuit and method for wireless information access thereof 有权
标题翻译：用于无线信息访问的三维集成电路及方法
公开(公告)号：US09086452B2
公开(公告)日：2015-07-21
申请号：US13572533
申请日：2012-08-10
申请人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
发明人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
IPC分类号： G01R31/28 , H01L23/02 , G06F17/50 , H01L23/00 , H01L25/065 , G01R31/302
CPC分类号： G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311
摘要： A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.
摘要翻译：提供了三维集成电路（3DIC）及其无线信息访问方法。所提出的3DIC包括半导体结构和形成在半导体结构上的无线功率器件（WPD），用于无线地接收用于操作从包括探测半导体结构，测试半导体结构和访问第一信息的组中选择的功能的功率从半导体结构。

4. 发明授权

US08643402B2 Phase frequency detector circuit 有权
标题翻译：相位检波电路
公开(公告)号：US08643402B2
公开(公告)日：2014-02-04
申请号：US13308274
申请日：2011-11-30
申请人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D13/00 , H03D3/00
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

5. 发明申请

US20130320553A1 NOVEL BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION 有权
标题翻译： 2.5D / 3D芯片包装应用的新颖的珠子
公开(公告)号：US20130320553A1
公开(公告)日：2013-12-05
申请号：US13481974
申请日：2012-05-29
申请人： Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU , Der-Chyang YEH , Chuei-Tang WANG
发明人： Feng Wei KUO , Huan-Neng CHEN , Chewn-Pu JOU , Der-Chyang YEH , Chuei-Tang WANG
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5227 , H01L23/552 , H01L2223/6616 , H01L2224/04105 , H01L2224/24137 , H01L2924/14 , H01L2924/15311 , H01L2924/18162
摘要： An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
摘要翻译：具有多层插入器的集成电路封装具有设置在插入件中的一个或多个金属布线珠，所述一个或多个金属布线珠中的每一个具有形成在所述插入件中的所述多层布线结构中的一层中的卷曲布线图案，以及连接到集成电路封装中的电力线的两个终端段，其中所述一个或多个金属布线珠作为功率噪声滤波器起作用。

6. 发明授权

US08456207B1 Lock detector and method of detecting lock status for phase lock loop 有权
标题翻译：锁定检测器和检测锁相环锁定状态的方法
公开(公告)号：US08456207B1
公开(公告)日：2013-06-04
申请号：US13297658
申请日：2011-11-16
申请人： Feng Wei Kuo , Kyle Yen , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Kyle Yen , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
摘要翻译：用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

7. 发明申请

US20130134553A1 INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES 审中-公开
标题翻译：具有噪声抑制特征的插座和半导体封装
公开(公告)号：US20130134553A1
公开(公告)日：2013-05-30
申请号：US13360958
申请日：2012-01-30
申请人： Feng Wei Kuo , Hui Yu Lee , Huan-Neng Chen , Yen-Jen Chen , Yu-Ling Lin , Chewn-Pu Jou
发明人： Feng Wei Kuo , Hui Yu Lee , Huan-Neng Chen , Yen-Jen Chen , Yu-Ling Lin , Chewn-Pu Jou
IPC分类号： H01L29/92 , H01L23/552 , H01L23/498
CPC分类号： H01L23/552 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/642 , H01L23/66 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0655 , H01L2223/6677 , H01L2224/131 , H01L2224/14135 , H01L2224/16225 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/19042 , H01L2924/19104 , H01L2924/014
摘要： Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
摘要翻译：插入器和半导体封装实施例提供了隔离和抑制电子噪声，例如半导体封装中的EM发射。插入器包括各种实施例中的屏蔽结构，屏蔽结构阻挡来自噪声源的电噪声与其它电信号或装置。在其他实施例中，屏蔽件包括固体结构和一些实施例以及去耦电容器。耦合结构包括多个包含在条中的焊球，其耦合部件并围绕并包含电噪声源。

8. 发明申请

US20120262216A1 UP-CONVERSION MIXER 有权
标题翻译：上变频混频器
公开(公告)号：US20120262216A1
公开(公告)日：2012-10-18
申请号：US13084885
申请日：2011-04-12
申请人： Huan-Neng CHEN , Ying-Ta LU , Mei-Show CHEN , Chewn-Pu JOU
发明人： Huan-Neng CHEN , Ying-Ta LU , Mei-Show CHEN , Chewn-Pu JOU
IPC分类号： G06G7/16 , G06G7/12
CPC分类号： H04L27/06 , G06G7/16 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0019 , H04L27/04
摘要： According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum.
摘要翻译：根据一些实施例，上变频混频器包括具有布置成提供输出的输出节点的混频器单元。输入级耦合到混频器单元并被布置成接收输入信号。混频器单元被配置为与输入信号的输入频率相比，产生具有上转换频率的输出。输入级被配置为减少输出的三阶谐波项，使得相对于输入功率的三阶谐波项的输出功率图具有局部最小值的陷波。

9. 发明授权

US09559053B2 Compact vertical inductors extending in vertical planes 有权
标题翻译：紧凑的垂直电感器在垂直平面上延伸
公开(公告)号：US09559053B2
公开(公告)日：2017-01-31
申请号：US13091440
申请日：2011-04-21
申请人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Huan-Neng Chen , Yu-Ling Lin , Chin-Wei Kuo , Mei-Show Chen , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号： H01F5/00 , H01F27/28 , H01L23/522 , H01F17/00
CPC分类号： H01F27/2804 , H01F17/0013 , H01F2017/002 , H01F2017/004 , H01F2027/2809 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
摘要翻译：器件包括衬底和衬底上的垂直电感器。垂直电感器包括由金属形成的多个部件，其中每个部件在与基板的主表面垂直的多个平面中的一个平面中延伸。金属线互连垂直电感器的多个部分中的相邻部分。

10. 发明授权

US09275950B2 Bead for 2.5D/3D chip packaging application 有权
标题翻译：珠子用于2.5D / 3D芯片封装应用
公开(公告)号：US09275950B2
公开(公告)日：2016-03-01
申请号：US13481974
申请日：2012-05-29
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
IPC分类号： H01L23/528 , H01L23/552 , H01L23/522
CPC分类号： H01L23/528 , H01L23/5227 , H01L23/552 , H01L2223/6616 , H01L2224/04105 , H01L2224/24137 , H01L2924/14 , H01L2924/15311 , H01L2924/18162
摘要： An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
摘要翻译：具有多层插入器的集成电路封装具有设置在插入件中的一个或多个金属布线珠，所述一个或多个金属布线珠中的每一个具有形成在所述插入件中的所述多层布线结构中的一层中的卷曲布线图案，以及连接到集成电路封装中的电力线的两个终端段，其中所述一个或多个金属布线珠作为功率噪声滤波器起作用。

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