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1. 发明申请

US20110057694A1 REGULATOR HAVING INTERLEAVED LATCHES 有权
标题翻译：具有互相锁定的调节器
公开(公告)号：US20110057694A1
公开(公告)日：2011-03-10
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： H03L7/06 , G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

2. 发明申请

US20110025379A1 LATCHED COMPARATOR AND METHODS THEREFOR 有权
标题翻译：锁定比较器及其方法
公开(公告)号：US20110025379A1
公开(公告)日：2011-02-03
申请号：US12534409
申请日：2009-08-03
申请人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
发明人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
IPC分类号： H03K5/22 , H03F3/45
CPC分类号： H03F3/45192 , H03F2203/45028
摘要： A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.
摘要翻译：比较器的比较周期包括预充电阶段和比较阶段。在预充电阶段期间，将比较器的节点预充电到限定的电压。此外，在预充电阶段期间，比较器的输入晶体管与节点分离。在比较阶段期间，输入电压通过输入晶体管耦合到节点。输入晶体管在预充电阶段和比较阶段都保持饱和，从而降低开关噪声。

3. 发明授权

US07948302B2 Regulator having interleaved latches 有权
标题翻译：具有交错锁存器的调节器
公开(公告)号：US07948302B2
公开(公告)日：2011-05-24
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

4. 发明申请

US20090251178A1 Ultra Low Power Servo-Controlled Single Clock Ramp Generator with Amplitude Independent to Clock Frequency 有权
标题翻译：超低功耗伺服控制单时钟斜坡发生器，具有独立于时钟频率的幅度
公开(公告)号：US20090251178A1
公开(公告)日：2009-10-08
申请号：US12098113
申请日：2008-04-04
申请人： Jung Hyun Choi , Fernando Chavez Porras
发明人： Jung Hyun Choi , Fernando Chavez Porras
IPC分类号： H03K4/06
CPC分类号： H03K4/50
摘要： A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.
摘要翻译：低功率伺服控制单时钟斜坡发生器（100）包括快速开关比较器（102），电荷泵（110）和电压 - 电流转换器（120），其连接以在脉冲比较的控制下提供反馈控制机构时钟信号（pulse_comp）和从单个输入时钟信号（clkin）产生的复位脉冲时钟信号（rst_pulse），使得在脉冲比较时钟信号和复位脉冲时钟信号中的脉冲之间存在明确的时间间隔，由此提供具有不受参考电压限制的稳定的频率无关幅度的斜坡信号（Vramp_out）。

5. 发明授权

US08143921B2 Latched comparator and methods therefor 有权
标题翻译：锁存比较器及其方法
公开(公告)号：US08143921B2
公开(公告)日：2012-03-27
申请号：US12534409
申请日：2009-08-03
申请人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
发明人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
IPC分类号： H03K5/22
CPC分类号： H03F3/45192 , H03F2203/45028
摘要： A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.
摘要翻译：比较器的比较周期包括预充电阶段和比较阶段。在预充电阶段期间，将比较器的节点预充电到限定的电压。此外，在预充电阶段期间，比较器的输入晶体管与节点分离。在比较阶段期间，输入电压通过输入晶体管耦合到节点。输入晶体管在预充电阶段和比较阶段都保持饱和，从而降低开关噪声。

6. 发明授权

US07746129B2 Ultra low power servo-controlled single clock ramp generator with amplitude independent to clock frequency 有权
标题翻译：超低功率伺服控制单时钟斜坡发生器，幅度与时钟频率无关
公开(公告)号：US07746129B2
公开(公告)日：2010-06-29
申请号：US12098113
申请日：2008-04-04
申请人： Jung Hyun Choi , Fernando Chavez Porras
发明人： Jung Hyun Choi , Fernando Chavez Porras
IPC分类号： H03K4/06
CPC分类号： H03K4/50
摘要： A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.
摘要翻译：低功率伺服控制单时钟斜坡发生器（100）包括快速开关比较器（102），电荷泵（110）和电压 - 电流转换器（120），其连接以在脉冲比较的控制下提供反馈控制机构时钟信号（pulse_comp）和从单个输入时钟信号（clkin）产生的复位脉冲时钟信号（rst_pulse），使得在脉冲比较时钟信号和复位脉冲时钟信号中的脉冲之间存在明确的时间间隔，由此提供具有不受参考电压限制的稳定的频率无关幅度的斜坡信号（Vramp_out）。

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