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1. 发明授权

US07948302B2 Regulator having interleaved latches 有权
标题翻译：具有交错锁存器的调节器
公开(公告)号：US07948302B2
公开(公告)日：2011-05-24
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

2. 发明申请

US20110057694A1 REGULATOR HAVING INTERLEAVED LATCHES 有权
标题翻译：具有互相锁定的调节器
公开(公告)号：US20110057694A1
公开(公告)日：2011-03-10
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： H03L7/06 , G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

3. 发明授权

US08830772B2 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US08830772B2
公开(公告)日：2014-09-09
申请号：US13524555
申请日：2012-06-15
申请人： Walter Luis Tercariol , Andre Luis Vilas Boas , Fernando Zampronho Neto
发明人： Walter Luis Tercariol , Andre Luis Vilas Boas , Fernando Zampronho Neto
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , H03F3/082
摘要： A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter (113) has an input terminal (115) and an OUT output node and a second transistor (125). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch (110) of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.
摘要翻译：读出放大器（100）包括第一和第二反相器（112和113）。第一反相器具有输入端（116）和OUT_B输出节点和第一晶体管（124）。第二反相器（113）具有输入端（115）和OUT输出节点和第二晶体管（125）。第一反相器的OUT_B输出节点耦合到第二反相器的输入端，第二反相器的OUT节点耦合到第一反相器的输入端。读出放大器不使用参考电流; 因此，读出放大器不需要参考电流发生器。读出放大器仅需要一个使能信号来复位读出放大器的锁存器（110）。当耦合到非易失性存储器元件时，输出节点处的电压指示存储在非易失性存储器元件中的位的逻辑电平。

4. 发明授权

US08935117B2 Circuit and method for measuring voltage 有权
标题翻译：用于测量电压的电路和方法
公开(公告)号：US08935117B2
公开(公告)日：2015-01-13
申请号：US13416892
申请日：2012-03-09
申请人： Walter Luis Tercariol , Richard T. L. Saez , Fernando Zampronho Neto , Ivan Carlos Ribeiro Nascimento
发明人： Walter Luis Tercariol , Richard T. L. Saez , Fernando Zampronho Neto , Ivan Carlos Ribeiro Nascimento
IPC分类号： G06F19/00 , G01R31/00 , G01R31/28 , G01R19/00 , G01R31/26 , G01R31/3185 , H01L29/78 , H01L29/417 , H03K17/082
CPC分类号： G01R31/2884 , G01R19/0084 , G01R31/2621 , G01R31/318511 , H01L29/41766 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7815 , H03K17/0822
摘要： A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.
摘要翻译：集成电路中的测试电路间接测量集成电路中其他电路的节点处的电压。测试电路包括具有控制电极的晶体管，耦合到第一焊盘的第一导电电极，耦合到电源的端子的第二导电电极和用于选择性地将控制电极耦合到节点之一的一个或多个开关和第二垫。一种方法包括当控制电极耦合到第二焊盘时确定漏极电流和晶体管的栅极电压之间的关系。当控制电极耦合到节点时，通过将通过晶体管的第一导电电极的电流相关联来确定节点处的电压。

5. 发明申请

US20130238273A1 CIRCUIT AND METHOD FOR MEASURING VOLTAGE 有权
标题翻译：用于测量电压的电路和方法
公开(公告)号：US20130238273A1
公开(公告)日：2013-09-12
申请号：US13416892
申请日：2012-03-09
申请人： Walter Luis TERCARIOL , Richard T. L. SAEZ , Fernando Zampronho NETO , Ivan Carlos Ribeiro NASCIMENTO
发明人： Walter Luis TERCARIOL , Richard T. L. SAEZ , Fernando Zampronho NETO , Ivan Carlos Ribeiro NASCIMENTO
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/2884 , G01R19/0084 , G01R31/2621 , G01R31/318511 , H01L29/41766 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7815 , H03K17/0822
摘要： A testing circuit (100) in an integrated circuit (102) indirectly measures a voltage at a node of other circuitry (104) in the integrated circuit. The testing circuit includes a transistor (120) having a control electrode (121), a first conducting electrode (122) coupled to a first pad (150), a second conducting electrode (123) coupled to a terminal of a power supply, and one or more switches (131 and 133) for selectively coupling the control electrode to one of the node and a second pad (140). A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.
摘要翻译：集成电路（102）中的测试电路（100）间接地测量集成电路中其它电路（104）的节点处的电压。测试电路包括具有控制电极（121）的晶体管（120），耦合到第一焊盘（150）的第一导电电极（122），耦合到电源端子的第二导电电极（123），以及一个或多个开关（131和133），用于选择性地将控制电极耦合到节点之一和第二垫（140）。一种方法包括当控制电极耦合到第二焊盘时确定漏极电流和晶体管的栅极电压之间的关系。当控制电极耦合到节点时，通过将通过晶体管的第一导电电极的电流相关联来确定节点处的电压。

6. 发明申请

US20120300552A1 CHARGE PUMP CIRCUIT WITH FAST START-UP 有权
标题翻译：充电泵电路快速启动
公开(公告)号：US20120300552A1
公开(公告)日：2012-11-29
申请号：US13113212
申请日：2011-05-23
申请人： Fernando Zampronho NETO , Walter Luis TERCARIOL
发明人： Fernando Zampronho NETO , Walter Luis TERCARIOL
IPC分类号： G11C11/34 , G05F3/02
CPC分类号： H02M3/073 , H02M1/36 , H02M2003/077
摘要： A charge pump circuit (300) includes a charge pump (330), and clocking circuitry that includes a clock generator (310) and a bypass circuit (320). The clocking circuitry generates clock signals and higher frequency alternative clock signals, for driving the charge pump. Upon start-up of the charge pump circuit and depending on a present value of an output voltage of the charge pump, the clocking circuitry couples to the charge pump either the alternative clock signals and not the clock signals, or the clock signals and not the alternative clock signals. Prior to completion of start-up of the charge pump circuit, at least two rows of pump unit cells are driven by a same alternative clock signal, thereby causing a pump unit cell in a row to charge/discharge at a same time as another pump unit cell in another row, thereby decreasing a start-up time of the charge pump circuit.
摘要翻译：电荷泵电路（300）包括电荷泵（330）和包括时钟发生器（310）和旁路电路（320）的时钟电路。时钟电路产生时钟信号和更高频率的替代时钟信号，用于驱动电荷泵。在启动电荷泵电路并根据电荷泵的输出电压的当前值的情况下，时钟电路将可选的时钟信号而不是时钟信号或时钟信号耦合到电荷泵，而不是时钟信号备用时钟信号。在电荷泵电路启动完成之前，至少两排泵单元由相同的备选时钟信号驱动，从而使泵单元电池与另一泵同时进行充放电单元电池，从而减少电荷泵电路的启动时间。

7. 发明授权

US08811108B2 Code coverage circuitry 有权
标题翻译：代码覆盖电路
公开(公告)号：US08811108B2
公开(公告)日：2014-08-19
申请号：US13195505
申请日：2011-08-01
申请人： Rafael M. Vilela , Walter Luis Tercariol , Fernando Zampronho Neto , Sandro A. P. Haddad
发明人： Rafael M. Vilela , Walter Luis Tercariol , Fernando Zampronho Neto , Sandro A. P. Haddad
IPC分类号： G11C11/24
CPC分类号： G11C29/12015 , G06F11/3676 , G11C7/16 , G11C8/08 , G11C2029/1202
摘要： A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.
摘要翻译：电路包括耦合到模拟线路覆盖电路（104）的存储器（130）。模拟线路覆盖电路包括多个缓冲器（151-154），其中每个缓冲器耦合到存储器的一个存储器位置，其中每个存储单元耦合到缓冲器的多个存储单元（161-164）多路复用器（170），其每个输入端耦合到一个二进制信元单元，以及耦合到多路复用器和模拟线路覆盖电路的输出端的模拟 - 数字转换器（180）。模拟线路覆盖电路存储表示访问存储器位置的次数的模拟电压，并输出表示其的信号。处理器（102）耦合到存储器和模拟线路覆盖电路，并且当处理器处于调试模式时，处理器使能模拟线路覆盖电路。

8. 发明申请

US20130336066A1 SENSE AMPLIFIER CIRCUIT 有权
标题翻译：感应放大器电路
公开(公告)号：US20130336066A1
公开(公告)日：2013-12-19
申请号：US13524555
申请日：2012-06-15
申请人： Walter Luis TERCARIOL , Andre Luis VILAS BOAS , Fernando Zampronho NETO
发明人： Walter Luis TERCARIOL , Andre Luis VILAS BOAS , Fernando Zampronho NETO
IPC分类号： G11C16/26 , H03F3/68 , H03F3/04
CPC分类号： G11C16/28 , H03F3/082
摘要： A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter (113) has an input terminal (115) and an OUT output node and a second transistor (125). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch (110) of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.
摘要翻译：读出放大器（100）包括第一和第二反相器（112和113）。第一反相器具有输入端（116）和OUT_B输出节点和第一晶体管（124）。第二反相器（113）具有输入端（115）和OUT输出节点和第二晶体管（125）。第一反相器的OUT_B输出节点耦合到第二反相器的输入端，第二反相器的OUT节点耦合到第一反相器的输入端。读出放大器不使用参考电流; 因此，读出放大器不需要参考电流发生器。读出放大器仅需要一个使能信号来复位读出放大器的锁存器（110）。当耦合到非易失性存储器元件时，输出节点处的电压指示存储在非易失性存储器元件中的位的逻辑电平。

9. 发明授权

US08462578B2 Charge pump circuit with fast start-up 有权
标题翻译：充电泵电路具有快速启动功能
公开(公告)号：US08462578B2
公开(公告)日：2013-06-11
申请号：US13113212
申请日：2011-05-23
申请人： Fernando Zampronho Neto , Walter Luis Tercariol
发明人： Fernando Zampronho Neto , Walter Luis Tercariol
IPC分类号： G11C8/00
CPC分类号： H02M3/073 , H02M1/36 , H02M2003/077
摘要： A charge pump circuit (300) includes a charge pump (330), and clocking circuitry that includes a clock generator (310) and a bypass circuit (320). The clocking circuitry generates clock signals and higher frequency alternative clock signals, for driving the charge pump. Upon start-up of the charge pump circuit and depending on a present value of an output voltage of the charge pump, the clocking circuitry couples to the charge pump either the alternative clock signals and not the clock signals, or the clock signals and not the alternative clock signals. Prior to completion of start-up of the charge pump circuit, at least two rows of pump unit cells are driven by a same alternative clock signal, thereby causing a pump unit cell in a row to charge/discharge at a same time as another pump unit cell in another row, thereby decreasing a start-up time of the charge pump circuit.
摘要翻译：电荷泵电路（300）包括电荷泵（330）和包括时钟发生器（310）和旁路电路（320）的时钟电路。时钟电路产生时钟信号和更高频率的替代时钟信号，用于驱动电荷泵。在启动电荷泵电路并根据电荷泵的输出电压的当前值的情况下，时钟电路将可选的时钟信号而不是时钟信号或时钟信号耦合到电荷泵，而不是时钟信号备用时钟信号。在电荷泵电路启动完成之前，至少两排泵单元由相同的备选时钟信号驱动，从而使泵单元电池与另一泵同时进行充放电单元电池，从而减少电荷泵电路的启动时间。

10. 发明申请

US20130033924A1 CODE COVERAGE CIRCUITRY 有权
标题翻译：代码覆盖电路
公开(公告)号：US20130033924A1
公开(公告)日：2013-02-07
申请号：US13195505
申请日：2011-08-01
申请人： Rafael M. VILELA , Walter Luis TERCARIOL , Fernando Zampronho NETO , Sandro A.P. HADDAD
发明人： Rafael M. VILELA , Walter Luis TERCARIOL , Fernando Zampronho NETO , Sandro A.P. HADDAD
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： G11C29/12015 , G06F11/3676 , G11C7/16 , G11C8/08 , G11C2029/1202
摘要： A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.
摘要翻译：电路包括耦合到模拟线路覆盖电路（104）的存储器（130）。模拟线路覆盖电路包括多个缓冲器（151-154），其中每个缓冲器耦合到存储器的一个存储器位置，其中每个存储单元耦合到缓冲器的多个存储单元（161-164）多路复用器（170），其每个输入端耦合到一个二进制信元单元，以及耦合到多路复用器和模拟线路覆盖电路的输出端的模拟 - 数字转换器（180）。模拟线路覆盖电路存储表示访问存储器位置的次数的模拟电压，并输出表示其的信号。处理器（102）耦合到存储器和模拟线路覆盖电路，并且当处理器处于调试模式时，处理器使能模拟线路覆盖电路。

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