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1. 发明授权

US07948302B2 Regulator having interleaved latches 有权
标题翻译：具有交错锁存器的调节器
公开(公告)号：US07948302B2
公开(公告)日：2011-05-24
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

2. 发明申请

US20110057694A1 REGULATOR HAVING INTERLEAVED LATCHES 有权
标题翻译：具有互相锁定的调节器
公开(公告)号：US20110057694A1
公开(公告)日：2011-03-10
申请号：US12555227
申请日：2009-09-08
申请人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
发明人： Fernando Zampronho NETO , Fernando Chavez Porras , Jon S. Choy , Walter Luis Tercariol
IPC分类号： H03L7/06 , G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).
摘要翻译：电荷泵系统（100）包括电荷泵（102）和包括用于提供时钟信号的时钟发生器（120）的调节器（101），耦合到时钟发生器的控制逻辑（130）和比较器（140），其耦合到所述电荷泵的输出。比较器包括由比较输出电压和参考电压的单个差分（203）级驱动的多个交错锁存器（211,212,213和214）。控制逻辑提供定时信号以使得每个锁存器在时钟信号的每个周期内的不同时间点上执行锁存动作，每个时间点相等间隔开。来自每个锁存器的输出耦合到输出级（205）。来自输出级的输出信号调节来自电荷泵的输出电压。在一个实施例中，电荷泵耦合到闪速存储器（190）。

3. 发明申请

US20110025379A1 LATCHED COMPARATOR AND METHODS THEREFOR 有权
标题翻译：锁定比较器及其方法
公开(公告)号：US20110025379A1
公开(公告)日：2011-02-03
申请号：US12534409
申请日：2009-08-03
申请人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
发明人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
IPC分类号： H03K5/22 , H03F3/45
CPC分类号： H03F3/45192 , H03F2203/45028
摘要： A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.
摘要翻译：比较器的比较周期包括预充电阶段和比较阶段。在预充电阶段期间，将比较器的节点预充电到限定的电压。此外，在预充电阶段期间，比较器的输入晶体管与节点分离。在比较阶段期间，输入电压通过输入晶体管耦合到节点。输入晶体管在预充电阶段和比较阶段都保持饱和，从而降低开关噪声。

4. 发明授权

US08143921B2 Latched comparator and methods therefor 有权
标题翻译：锁存比较器及其方法
公开(公告)号：US08143921B2
公开(公告)日：2012-03-27
申请号：US12534409
申请日：2009-08-03
申请人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
发明人： Fernando Z. Neto , Fernando Chavez Porras , Jon S. Choy , Walter Luis L. Tercariol
IPC分类号： H03K5/22
CPC分类号： H03F3/45192 , H03F2203/45028
摘要： A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.
摘要翻译：比较器的比较周期包括预充电阶段和比较阶段。在预充电阶段期间，将比较器的节点预充电到限定的电压。此外，在预充电阶段期间，比较器的输入晶体管与节点分离。在比较阶段期间，输入电压通过输入晶体管耦合到节点。输入晶体管在预充电阶段和比较阶段都保持饱和，从而降低开关噪声。

5. 发明授权

US09224486B1 Control gate driver for use with split gate memory cells 有权
标题翻译：控制栅极驱动器用于分离栅极存储单元
公开(公告)号：US09224486B1
公开(公告)日：2015-12-29
申请号：US14310585
申请日：2014-06-20
申请人： Jon S. Choy , Anirban Roy
发明人： Jon S. Choy , Anirban Roy
IPC分类号： G11C16/04 , G11C16/24 , G11C16/26 , G11C16/22 , G11C16/12 , G11C16/34
CPC分类号： G11C16/24 , G11C16/12 , G11C16/225 , G11C16/26 , G11C16/3445 , G11C16/3459
摘要： A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate.
摘要翻译：用于驱动分闸器非易失性存储单元的控制栅极的电路可以包括开关电流源; 第一晶体管，其具有耦合到所述开关电流源的电流电极和耦合到电压源的控制电极; 第二晶体管，其具有耦合到所述开关电流源的第二节点的电流电极，以及耦合到第三电压源的控制电极; 第三晶体管，其具有耦合到所述第二晶体管的控制电极，耦合到所述第一晶体管的电流电极和第四开关电压源; 以及第四晶体管，其具有耦合到所述第一开关电压源的电流电极，耦合到所述开关电流源的控制电极和在驱动器电压节点处耦合到所述第二晶体管的第二电流电极，其中所述驱动器电压节点可操作以驱动控制门。

6. 发明授权

US08929168B2 Sense amplifier voltage regulator 有权
标题翻译：感应放大器电压调节器
公开(公告)号：US08929168B2
公开(公告)日：2015-01-06
申请号：US13780969
申请日：2013-02-28
申请人： Jon S. Choy
发明人： Jon S. Choy
IPC分类号： G11C7/00 , G11C7/06 , G11C5/14 , G11C11/4074
CPC分类号： G11C7/06 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/065 , G11C11/4074 , G11C16/28 , G11C16/30
摘要： A memory is disclosed that includes a plurality of memory cells, a plurality of sense amplifiers for reading data of the memory cells, and a voltage regulator coupled to the plurality of sense amplifiers. The voltage regulator includes a reference sense amplifier, a current injector, and a current injector control circuit. The current injector control circuit controls an amount of current provided by the current injector to an output node of the voltage regulator based on a voltage of the reference sense amplifier.
摘要翻译：公开了一种存储器，其包括多个存储单元，用于读取存储单元的数据的多个读出放大器以及耦合到多个读出放大器的电压调节器。电压调节器包括参考读出放大器，电流注入器和电流注入器控制电路。电流注入器控制电路基于参考读出放大器的电压来控制由电流注入器提供给电压调节器的输出节点的电流量。

7. 发明授权

US08351276B2 Soft program of a non-volatile memory block 有权
标题翻译：非易失性存储器块的软程序
公开(公告)号：US08351276B2
公开(公告)日：2013-01-08
申请号：US12835309
申请日：2010-07-13
申请人： Jon S. Choy , Chen He , Michael A. Sadd
发明人： Jon S. Choy , Chen He , Michael A. Sadd
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/0483 , G11C16/16
摘要： A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
摘要翻译：一种方法包括擦除位并识别被擦除过度擦除的位。已经被擦除的位的第一个子集是软编程的。测量第一个子集的软编程的结果。选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。已经被擦除的位的第二个子集是软编程的。软编程将初始电压条件应用于位的第二子集中的位。第二子集包括当选择步骤发生时仍然被擦除的比特。结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

8. 发明申请

US20120014179A1 SOFT PROGRAM OF A NON-VOLATILE MEMORY BLOCK 有权
标题翻译：非易失性存储器块的软件程序
公开(公告)号：US20120014179A1
公开(公告)日：2012-01-19
申请号：US12835309
申请日：2010-07-13
申请人： Jon S. Choy , Chen He , Michael A. Sadd
发明人： Jon S. Choy , Chen He , Michael A. Sadd
IPC分类号： G11C16/04
CPC分类号： G11C16/3468 , G11C16/0483 , G11C16/16
摘要： A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
摘要翻译：一种方法包括擦除位并识别被擦除过度擦除的位。已经被擦除的位的第一个子集是软编程的。测量第一个子集的软编程的结果。选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。已经被擦除的位的第二个子集是软编程的。软编程将初始电压条件应用于位的第二子集中的位。第二子集包括当选择步骤发生时仍然被擦除的比特。结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

9. 发明授权

US07724603B2 Method and circuit for preventing high voltage memory disturb 有权
标题翻译：防止高压存储器干扰的方法和电路
公开(公告)号：US07724603B2
公开(公告)日：2010-05-25
申请号：US11833545
申请日：2007-08-03
申请人： Jon S. Choy , Yanzhuo Wang
发明人： Jon S. Choy , Yanzhuo Wang
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/143 , G11C5/145
摘要： A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The higher voltages are used to operate the memory array. Operation of the oscillator is controlled with the memory control logic when the logic power domain is at least at a first level or value. The oscillator is disabled when the logic power domain is below the first level. The disabling of the oscillator has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array when they may not be properly controlled.
摘要翻译：电路和方法减少由两个电源电压中的一个下降到预定值以下的存储器阵列中的干扰。存储器控制逻辑使用逻辑电源域进行操作。响应于振荡器振荡而产生比逻辑功率域的电压更高的电压。较高的电压用于操作存储器阵列。当逻辑功率域至少处于第一级或值时，通过存储器控制逻辑来控制振荡器的操作。当逻辑电源域低于第一级时，振荡器被禁止。振荡器的禁用具有防止产生较高电压的效果。这有助于防止较高的电压在它们可能未被适当地控制时到达存储器阵列。

10. 发明授权

US07640389B2 Non-volatile memory having a multiple block erase mode and method therefor 有权
标题翻译：具有多块擦除模式的非易失性存储器及其方法
公开(公告)号：US07640389B2
公开(公告)日：2009-12-29
申请号：US11364129
申请日：2006-02-28
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00
CPC分类号： G06F12/0246
摘要： A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.
摘要翻译：非易失性存储器可以具有并行擦除多个块，用于相对较少数量的擦除操作。这样可以节省用户设置存储器的时间，因为擦除操作相对较慢。并行擦除的问题涉及具有不同程序/擦除历史的不同块，结果是具有不同历史的块被擦除不同。因此，在执行预定数量的擦除周期之后，防止并行擦除的能力。这通过允许并行擦除操作直到预定数量的擦除操作被计数来实现。在达到预定数量之后，产生并行擦除模式禁止信号，以防止进一步的并行擦除周期。计数和预定数量被保持在用户无法访问的非易失性存储器的小块中。

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