专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130285147A1 COMPACT TID HARDENING NMOS DEVICE AND FABRICATION PROCESS 审中-公开
标题翻译：紧凑的钽硬化NMOS器件和制造工艺
公开(公告)号：US20130285147A1
公开(公告)日：2013-10-31
申请号：US13870860
申请日：2013-04-25
申请人： Fethi Dhaoui
发明人： Fethi Dhaoui
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66477 , H01L29/66568 , H01L29/6659 , H01L29/7836
摘要： A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.
摘要翻译：辐射硬化晶体管形成在p型半导体本体中，该半导体主体具有掺杂到第一电平的有源区，并被介质填充的浅沟槽隔离区包围。 N型源极/漏极区域设置在有源区域中并间隔开以限定沟道。栅极设置在通道上方，并且与源极/漏极区域自对准。第一和第二p型区域设置在源极/漏极区域之一的任一侧上的p型半导体本体中，并且被掺杂到高于第一掺杂水平的第二电平。第一和第二p型区域与栅极的第一侧边缘自对准并向外延伸。栅极的端部延伸超过第一和第二p型区域。

2. 发明授权

US07697330B1 Non-volatile memory array having drain-side segmentation for an FPGA device 有权
标题翻译：具有用于FPGA器件的漏极侧分割的非易失性存储器阵列
公开(公告)号：US07697330B1
公开(公告)日：2010-04-13
申请号：US11961203
申请日：2007-12-20
申请人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
发明人： Vidyahara Bellippady , Santosh Yachareni , Fethi Dhaoui , Zhigang Wang
IPC分类号： G11C16/00
CPC分类号： G11C16/0441
摘要： A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
摘要翻译：用于FPGA的非易失性存储器阵列包括以行和列排列并分成多个行段的多个存储单元。每个段中的每个非易失性存储器晶体管的源极耦合到一个共同的源极线。列分段线与阵列的每个段相关联，并且被耦合到段中的每个非易失性存储器晶体管的漏极。段选择晶体管耦合在每个列分段线与其相关联的列线之间，并且高电压驱动晶体管耦合到每个列线。

3. 发明授权

US07430137B2 Non-volatile memory cells in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的非易失性存储单元
公开(公告)号：US07430137B2
公开(公告)日：2008-09-30
申请号：US11868694
申请日：2007-10-08
申请人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
发明人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
IPC分类号： G11C16/02 , G11C5/02 , G11C5/06 , G06F7/38 , H03K19/173 , H03K19/177 , H03K19/94
CPC分类号： H03K19/1776 , G11C16/0441 , H03K19/17736 , H03K19/1778
摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.
摘要翻译：非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。

4. 发明授权

US08633548B2 Non-volatile programmable memory cell and array for programmable logic array 有权
标题翻译：用于可编程逻辑阵列的非易失性可编程存储单元和阵列
公开(公告)号：US08633548B2
公开(公告)日：2014-01-21
申请号：US12894441
申请日：2010-09-30
申请人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
发明人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
IPC分类号： H01L29/76
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/105 , H01L27/11807
摘要： A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
摘要翻译：适用于可编程逻辑阵列的非易失性可编程存储单元包括与第二导电类型的易失性MOS晶体管串联的第一导电类型的非易失性MOS晶体管。非挥发性MOS晶体管可以是诸如闪存晶体管的浮动栅极晶体管，或者可以是诸如浮动电荷捕获SONOS，MONOS晶体管或纳米晶体管的另一种类型的非易失性晶体管。可以通过将其栅极或输入耦合到非易失性MOS晶体管和易失性MOS晶体管之间的公共连接来驱动易失性MOS晶体管，反相器或缓冲器。

5. 发明申请

US20100044768A1 REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS 有权
标题翻译：降低辐射耐受非挥发性晶体管存储器细胞
公开(公告)号：US20100044768A1
公开(公告)日：2010-02-25
申请号：US12196978
申请日：2008-08-22
申请人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
发明人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/66825 , H01L29/66833
摘要： An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
摘要翻译：无边形单晶体管闪存阵列包括具有覆盖有源区域的两个多晶硅栅极层的晶体管。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。无刃双晶体管可编程存储器包括具有两个有源器件的存储器单元。两个多晶硅栅极层覆盖两个有源区，并在两个有源器件之间共享。其中一个器件用于编程和擦除单元，而另一个用作可编程逻辑器件中的可编程开关。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。

6. 发明授权

US07538379B1 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07538379B1
公开(公告)日：2009-05-26
申请号：US11303865
申请日：2005-12-16
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

7. 发明授权

US07482218B1 Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge 有权
标题翻译：低电容输入/输出和静电放电电路，用于保护集成电路免受静电放电
公开(公告)号：US07482218B1
公开(公告)日：2009-01-27
申请号：US11677441
申请日：2007-02-21
申请人： John McCollum , Fethi Dhaoui
发明人： John McCollum , Fethi Dhaoui
IPC分类号： H01L21/8238
CPC分类号： H01L29/1083 , H01L27/0266 , H01L29/7833
摘要： A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to said first conductivity type is disposed in the well. A pair of opposed source regions doped to the second conductivity type are disposed in the well and are electrically coupled together. They are separated from opposing outer edges of the drain region by channels. A pair of gates are electrically coupled together and disposed above and insulated from the channels. A region of the well disposed below the drain is doped so as to reduce capacitive coupling between the drain and the well.
摘要翻译：一种形成在第一导电类型的半导体衬底上的晶体管，其形成在衬底中，并且掺杂有第一导电类型的杂质水平高于衬底的杂质水平。掺杂到与所述第一导电类型相反的第二导电类型的漏极设置在阱中。掺杂到第二导电类型的一对相对的源极区域设置在阱中并且电耦合在一起。它们通过通道与漏极区域的相对的外边缘分离。一对门电耦合在一起并设置在通道上方并与通道绝缘。掺杂在漏极下方的阱的区域被掺杂以便减小漏极和阱之间的电容耦合。

8. 发明申请

US20080169498A1 NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY 失效
标题翻译：非易失可编程存储器单元和阵列可编程逻辑阵列
公开(公告)号：US20080169498A1
公开(公告)日：2008-07-17
申请号：US12054633
申请日：2008-03-25
申请人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Wilkinson
发明人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Wilkinson
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/105 , H01L27/11807
摘要： A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
摘要翻译：适用于可编程逻辑阵列的非易失性可编程存储单元包括与第二导电类型的易失性MOS晶体管串联的第一导电类型的非易失性MOS晶体管。非挥发性MOS晶体管可以是诸如闪存晶体管的浮动栅极晶体管，或者可以是诸如浮动电荷捕获SONOS，MONOS晶体管或纳米晶体管的另一种类型的非易失性晶体管。可以通过将其栅极或输入耦合到非易失性MOS晶体管和易失性MOS晶体管之间的公共连接来驱动易失性MOS晶体管，反相器或缓冲器。

9. 发明授权

US07906805B2 Reduced-edge radiation-tolerant non-volatile transistor memory cells 有权
标题翻译：降低辐射耐受性的非易失性晶体管存储单元
公开(公告)号：US07906805B2
公开(公告)日：2011-03-15
申请号：US12196978
申请日：2008-08-22
申请人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
发明人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/66825 , H01L29/66833
摘要： An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
摘要翻译：无边形单晶体管闪存阵列包括具有覆盖有源区域的两个多晶硅栅极层的晶体管。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。无刃双晶体管可编程存储器包括具有两个有源器件的存储器单元。两个多晶硅栅极层覆盖两个有源区，并在两个有源器件之间共享。其中一个器件用于编程和擦除单元，而另一个用作可编程逻辑器件中的可编程开关。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。

10. 发明授权

US07898018B2 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07898018B2
公开(公告)日：2011-03-01
申请号：US12359481
申请日：2009-01-26
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式