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1. 发明申请

US20200211653A1 FLASH MEMORY AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：US20200211653A1
公开(公告)日：2020-07-02
申请号：US16279046
申请日：2019-02-19
申请人： GigaDevice Semiconductor (Beijing) Inc.
发明人： Minyi CHEN
IPC分类号： G11C16/26 , G11C16/04 , G11C16/08 , G06F11/10 , G11C29/52
摘要： Provided are a flash memory and an operation method thereof. The flash memory includes a memory cell array, a controller and a register. The register stores read parameters that include a read voltage value and a read pass voltage value. The controller is configured to perform the read operation on a selected page according to the read parameters to read out the raw data stored in the selected page, determine whether the raw data includes an error bit, and in response to determining that the raw data includes the error bit, update the read parameters by decreasing the read voltage value and/or increasing the read pass voltage value.

2. 发明授权

US09396798B2 Enhanced flash chip and method for packaging chip 有权
标题翻译：增强闪存芯片和封装芯片的方法
公开(公告)号：US09396798B2
公开(公告)日：2016-07-19
申请号：US14647092
申请日：2013-06-24
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Hong Hu , Qingming Shu , Sai Zhang , Jianjun Zhang , Jiang Liu
IPC分类号： G11C11/34 , G11C16/10 , G11C16/26 , H01L25/18 , H01L23/00 , H01L25/00 , H01L23/498 , H01L25/065 , G11C5/04
CPC分类号： G11C16/10 , G11C5/04 , G11C16/26 , H01L23/49838 , H01L23/57 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05554 , H01L2224/451 , H01L2224/48145 , H01L2224/48227 , H01L2224/4911 , H01L2224/49171 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/1438 , H01L2224/43 , H01L2924/00012
摘要： An enhanced Flash chip and a method for packaging chip, wherein the enhanced Flash chip comprising: a FLASH and a RPMC, packaged integrally; the FLASH and the RPMC each comprising: a first internal IO pin and a second internal IO pin; the FLASH and the RPMC being further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH or the RPMC and the other end of which is mutually connected to the first internal IO pin of the RPMC or the FLASH; the second internal IO pin of the FLASH and the second internal IO pin of the RPMC being mutually connected. The enhanced Flash chip provided in the present application may effectively reduce design complexity and chip manufacturing cost, avoid the crossing of the metal lead wires in the chip package, and increase the yield of chip packages.
摘要翻译：一种增强型闪存芯片和一种用于封装芯片的方法，其中增强型闪存芯片包括：一体化封装的FLASH和RPMC; 所述FLASH和RPMC各自包括：第一内部IO引脚和第二内部IO引脚; FLASH和RPMC还设有跳线窗口，其一端相互连接到FLASH或RPMC的第一内部IO引脚，另一端相互连接到RPMC的第一内部IO引脚或FLASH; FLASH的第二个内部IO引脚和RPMC的第二个内部IO引脚相互连接。本申请中提供的增强型闪存芯片可以有效地降低设计复杂性和芯片制造成本，避免芯片封装中金属引线的交叉，并提高芯片封装的产量。

3. 发明授权

US10521157B2 Jump page cache read method in NAND flash memory and NAND flash memory 有权
公开(公告)号：US10521157B2
公开(公告)日：2019-12-31
申请号：US15871142
申请日：2018-01-15
申请人： GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC. , GIGADEVICE SEMICONDUCTOR (BEIJING) INC. , GIGADEVICE SEMICONDUCTOR (HEFEI) INC.
发明人： Minyi Chen
IPC分类号： G06F3/06 , G06F12/0893
摘要： A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.

4. 发明授权

US10289303B2 Flash controller and control method for flash controller 有权
公开(公告)号：US10289303B2
公开(公告)日：2019-05-14
申请号：US15506247
申请日：2015-01-30
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Baokui Li , Jinghua Wang , Nanfei Wang
IPC分类号： G06F3/06 , G06F12/14 , G06F21/60 , G11C16/22 , G06F21/79
摘要： A flash controller and a control method for the flash controller. The flash controller comprises an instruction bus interface, a data bus interface, a configuration register, an erase access filter module, a read/write access filter module and a flash control module. The read/write access filter module is configured to receive control information and determine whether the read/write access is sent to the flash control module or not. The erase access filter module is configured to receive control information and determine whether the erase access is sent to the flash control module or not. The flash control module is configured to complete an access to a flash memory. The present disclosure is used to protect programs from being stolen by a client, and also protect against a situation where companies collaboratively developing a program are able to steal programs from one another.

5. 发明授权

US10102155B2 Method and device of information protection for micro control unit chip 有权
公开(公告)号：US10102155B2
公开(公告)日：2018-10-16
申请号：US15505926
申请日：2015-01-26
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Baokui Li , Jinghua Wang , Nanfei Wang
IPC分类号： G06F12/14 , G06F21/79 , G06F21/85
摘要： The disclosure discloses a method and a device of information protection for a micro control unit (MCU) chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory; the flash controller is used to divide the user area into a first sub-area and a second sub-area; the method comprising: when the instruction bus accesses the user area, determining, whether the instruction bus accesses the first sub-area; if yes, entering the first sub-area working state; in the first sub-area working state, if the instruction bus accesses the second sub-area, entering the transition state; determining whether the time at transition state reaches a preset waiting time; if yes, entering the second sub-area working state; the disclosure is used to protect program from being stolen by users and prevent the cooperative companies stealing program from each other.

6. 发明授权

US09836236B2 SPI interface enhanced flash chip and chip packaging method 有权
公开(公告)号：US09836236B2
公开(公告)日：2017-12-05
申请号：US14412205
申请日：2013-07-15
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Qingming Shu , Hong Hu , Sai Zhang , Jianjun Zhang , Jiang Liu , Ronghua Pan
IPC分类号： G11C5/06 , G06F3/06 , H01L25/00 , G06F13/42 , H01L23/00
CPC分类号： G06F3/0626 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F13/4291 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/32145 , H01L2224/45144 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/1438 , H01L2924/00012 , H01L2924/00
摘要： An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.

7. 发明授权

US09490026B2 Nonvolatile memory erasure method and device 有权
标题翻译：非易失性存储器擦除方法和装置
公开(公告)号：US09490026B2
公开(公告)日：2016-11-08
申请号：US14897646
申请日：2014-04-24
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Hong Hu , Linkai Wang
IPC分类号： G11C16/06 , G11C16/34 , G11C16/16 , G11C16/14 , G11C16/28 , G11C16/10
CPC分类号： G11C16/3459 , G11C16/107 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3477
摘要： Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process.
摘要翻译：公开了用于解决不必要的时间消耗和当前擦除操作的复杂处理的问题的非易失性存储器擦除方法和装置。该方法包括：在接收到擦除指令之后，对与擦除指令相对应的目标擦除区进行预读验证; 如果预读验证通过，则对目标擦除区域执行擦除操作; 如果不是，则对目标擦除区域进行预编程验证，并且在预编程验证通过之后，对目标擦除区域执行擦除操作。本申请的方法可以在擦除操作之前确保目标擦除区域处于全擦除状态，从而消除不必要的预编程验证过程，从而节省擦除时间并简化擦除处理。

8. 发明申请

US20220076758A1 NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF AND ELECTRONIC DEVICE 有权
公开(公告)号：US20220076758A1
公开(公告)日：2022-03-10
申请号：US17187922
申请日：2021-03-01
申请人： Gigadevice Semiconductor (Beijing) Inc.
发明人： Minyi CHEN
IPC分类号： G11C16/16 , G11C16/26 , G11C16/08 , G11C16/30 , G11C16/34
摘要： A non-volatile memory includes a plurality of blocks and a controller. Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of storage units. The controller is configured to perform: receiving an erase command for a target block of the plurality of blocks; executing a read operation on each page of the target block; and executing a first erase operation to apply word line voltages to the plurality of pages, where the word line voltages are determined by a read result of the read operation of each page. An operation method of a non-volatile memory and an electronic device are also provided.

9. 发明授权

US10592644B2 Information protection method and device based on a plurality of sub-areas for MCU chip 有权
公开(公告)号：US10592644B2
公开(公告)日：2020-03-17
申请号：US15505616
申请日：2015-01-30
申请人： GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
发明人： Baokui Li , Jinghua Wang , Nanfei Wang
IPC分类号： G06F3/06 , G06F21/12 , G06F12/14 , G06F21/78 , G06F13/42 , G06F21/85 , G06F21/53 , G06F13/40
摘要： An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.

10. 发明授权

US10546644B2 NAND flash memory and method for destroying information from the NAND flash memory 有权
公开(公告)号：US10546644B2
公开(公告)日：2020-01-28
申请号：US15857643
申请日：2017-12-29
申请人： GigaDevice Semiconductor (Beijing) Inc.
发明人： Minyi Chen
IPC分类号： G11C16/16 , G11C16/30
摘要： The present application provides a NAND flash memory, comprising: a control unit, which includes a signal receiving unit, a voltage boosted circuit and a flash array; and a power source supplying power to the control unit; wherein when the voltage boosted circuit receives an erase signal from the signal receiving unit, the voltage boosted circuit exerts a device erase pulse whose magnitude is larger than an initial voltage to blocks of the flash array to permanently erase data in the blocks; the blocks include power-on read blocks. By removing data from at least power-on read blocks, the present invention discloses a scheme for permanently destroying the NAND flash memory.

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