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1. 发明申请

US20170116849A1 CONTROLLING RIGHT-OF-WAY FOR PRIORITY VEHICLES 审中-公开
公开(公告)号：US20170116849A1
公开(公告)日：2017-04-27
申请号：US14918776
申请日：2015-10-21
申请人： Global Foundries Inc.
发明人： Eric A. Foreman , Sudeep Mandal
IPC分类号： G08G1/00 , G01C21/34
CPC分类号： G08G1/0965 , G01C21/3407 , G01C21/3697 , G08G1/087
摘要： Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.

2. 发明申请

US20170054005A1 FINFET PCM ACCESS TRANSISTOR HAVING GATE-WRAPPED SOURCE AND DRAIN REGIONS 有权
公开(公告)号：US20170054005A1
公开(公告)日：2017-02-23
申请号：US14953702
申请日：2015-11-30
申请人： GLOBAL FOUNDRIES INC.
发明人： Chung H. Lam , Chung-Hsun Lin , Darsen D. Lu , Philip J. Oldiges
IPC分类号： H01L29/66 , H01L27/24 , H01L21/311 , H01L21/8234 , H01L29/423
CPC分类号： H01L27/2436 , H01L21/31105 , H01L21/823431 , H01L21/823456 , H01L29/0847 , H01L29/41791 , H01L29/42376 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L45/06
摘要： Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

3. 发明授权

US09455203B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US09455203B2
公开(公告)日：2016-09-27
申请号：US14992739
申请日：2016-01-11
申请人： International Business Machines Corporation , Global Foundries Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/02 , H01L29/161 , H01L29/10
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。可以在高k电介质上形成伪栅极结构，并被蚀刻以在NMOS区域上形成开口，并且在PMOS区域上形成开口。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

4. 发明申请

US20160146879A1 METHODS, APPARATUS AND SYSTEM FOR VOLTAGE RAMP TESTING 有权
标题翻译：方法，电压测试仪器和系统
公开(公告)号：US20160146879A1
公开(公告)日：2016-05-26
申请号：US14553863
申请日：2014-11-25
申请人： GLOBAL FOUNDRIES INC. , International Business Machines Corporation
发明人： Suresh Uppal , Andreas Kerber , William McMahon , Eduard A. Cartier
IPC分类号： G01R31/14 , G01R31/28 , G01R31/26
CPC分类号： G01R31/14 , G01R31/2879
摘要： At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.
摘要翻译：本文公开的至少一种方法和系统涉及集成电路的测试。提供具有至少一个晶体管和至少一个电介质层的器件。在第一时间段期间提供第一电压以对器件进行压力测试。在第二时间期间提供第二电压，用于对作为第一电压的结果的电荷积累的至少一部分进行放电。第二电压具有与第一电压相反的极性。在第三时间段期间提供感测功能以确定压力测试的结果。获取，存储和/或发送与基于压力测试的结果的介电层击穿有关的数据。

5. 发明授权

US09280682B2 Automated management of private information 有权
标题翻译：自动管理私人信息
公开(公告)号：US09280682B2
公开(公告)日：2016-03-08
申请号：US14362635
申请日：2012-09-20
申请人： GLOBAL FOUNDRIES INC.
发明人： Kiriyama Hayato , Tomohiro Shioya , Tadashi Tsumura
IPC分类号： G06F21/60 , G06F21/62
CPC分类号： G06F21/6218 , G06F21/604 , G06F21/6245
摘要： A private information management apparatus, a method, and a program that allows individual users to easily set and apply their privacy rules. A private information management apparatus receives setting data from a user terminal and creates a privacy rule that defines a condition for restricting disclosure of private information and a restriction method. If undisclosed image data contains private information of a user, the private information management apparatus extracts metadata contained in this undisclosed image data, and determines whether or not the metadata satisfies the condition for restricting disclosure of the private information. If it is determined that the condition is satisfied, the private information management apparatus executes the restriction method defined by the privacy rule.
摘要翻译：私人信息管理装置，方法和程序，允许个人用户容易地设置和应用其隐私规则。专用信息管理装置从用户终端接收设定数据，创建限定私人信息公开条件和限制方式的隐私规则。如果未公开的图像数据包含用户的私人信息，则私人信息管理装置提取包含在该未公开的图像数据中的元数据，并且确定元数据是否满足限制私人信息公开的条件。如果确定满足条件，则私人信息管理装置执行由隐私规则定义的限制方法。

6. 发明申请

US20160049514A1 GATE STACK AND CONTACT STRUCTURE 有权
公开(公告)号：US20160049514A1
公开(公告)日：2016-02-18
申请号：US14924925
申请日：2015-10-28
申请人： GLOBAL FOUNDRIES Inc.
发明人： Hui ZANG
IPC分类号： H01L29/78 , H01L29/06 , H01L29/49 , H01L29/45 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7851 , H01L21/02057 , H01L21/02112 , H01L21/283 , H01L21/76834 , H01L21/76897 , H01L21/823418 , H01L29/0653 , H01L29/41775 , H01L29/41791 , H01L29/4238 , H01L29/45 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A process for fabrication of semiconductor devices, particularly FinFETs, having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

7. 发明申请

US20160013050A1 INTEGRATED CIRCUITS WITH AN INSULTATING LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS 有权
标题翻译：具有绝缘层的集成电路和用于生产这种集成电路的方法
公开(公告)号：US20160013050A1
公开(公告)日：2016-01-14
申请号：US14325500
申请日：2014-07-08
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Ronny Pfutzner , Andreia Ioana Popa , Christof Streck
IPC分类号： H01L21/02 , H01L23/532 , H01L23/522 , H01L21/768 , H01L23/528
CPC分类号： H01L21/02318 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02323 , H01L21/02337 , H01L21/3105 , H01L21/76802 , H01L21/7682 , H01L21/76826 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for producing the same are provided. A method of producing the integrated circuits includes forming an insulating layer overlying a substrate. The insulating layer includes a first composition that includes silicon oxide and a porogen. The porogen is removed from the first composition to form a second composition that includes a pore, where the second composition has a dielectric constant lower than that of the first composition. An insulating layer mechanical property desired range is determined, where the second composition has an insulating material mechanical property outside of the insulating layer mechanical property desired range. The second composition is altered to form a third composition, where the third composition has the insulating layer mechanical property within the insulating layer mechanical property desired range.
摘要翻译：提供了集成电路及其制造方法。制造集成电路的方法包括形成覆盖在基板上的绝缘层。绝缘层包括包含氧化硅和致孔剂的第一组合物。造孔剂从第一组合物中除去以形成包含孔的第二组合物，其中第二组合物的介电常数低于第一组合物的介电常数。确定绝缘层机械性能期望范围，其中第二组合物具有在绝缘层机械性能期望范围之外的绝缘材料机械性能。改变第二组合物以形成第三组合物，其中第三组合物在绝缘层机械性能期望范围内具有绝缘层机械性能。

8. 发明授权

US09153534B2 Semiconductor fuse with enhanced post-programming resistance 有权
标题翻译：半导体保险丝具有增强的后编程电阻
公开(公告)号：US09153534B2
公开(公告)日：2015-10-06
申请号：US14517407
申请日：2014-10-17
申请人： GLOBAL FOUNDRIES Inc.
发明人： Andreas Kurz , Maciej Wiatr
IPC分类号： H01L29/78 , H01L23/525 , H01L21/265
CPC分类号： H01L23/5256 , H01L21/26506 , H01L2924/0002 , H01L2924/00
摘要： Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
摘要翻译：半导体熔丝的后编程电阻通过使用注入来形成非晶硅层并分解下面的高金属/金属栅极来增强。实施例包括在硅衬底中形成浅沟槽隔离（STI）区域，介电层在STI区上形成金属栅极，电介质层，在所述金属栅极上形成多晶硅层，执行注入以将所述多晶硅层转换成非晶硅层，其中所述注入破坏所述金属栅极，以及在所述非晶硅层上形成硅化物。通过分解金属栅极，消除了通过金属栅极的熔丝触点的电连接。

9. 发明授权

US09041118B2 Replacement metal gate structure for CMOS device 有权
标题翻译： CMOS器件替代金属栅极结构
公开(公告)号：US09041118B2
公开(公告)日：2015-05-26
申请号：US14500914
申请日：2014-09-29
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70 , H01L27/092 , H01L29/49 , H01L29/423
CPC分类号： H01L27/0922 , H01L21/02697 , H01L21/823842 , H01L21/823857 , H01L29/4236 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.
摘要翻译：一种CMOS器件，其在nFET部分和pFET部分之间包括nFET部分，pFET部分和层间电介质。 nFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，直接物理接触的第二氮化钛层其中阻挡层和填充凹槽的其余部分的栅极金属。 pFET部分具有栅极结构，其具有填充有共形高k电介质的凹部，高k电介质上的第一氮化钛层，第一氮化钛层上的阻挡层，阻挡层上的第二氮化钛层与第二氮化钛层直接物理接触的第三氮化钛层和填充凹槽的其余部分的栅极金属。

10. 发明申请

US20150091068A1 GATE ELECTRODE WITH A SHRINK SPACER 有权
标题翻译：带有收缩间隙的门电极
公开(公告)号：US20150091068A1
公开(公告)日：2015-04-02
申请号：US14043181
申请日：2013-10-01
申请人： GLOBAL FOUNDRIES Inc.
发明人： Tom Hasche , Sven Beyer , Gerhard Lembach , Alexander Ebermann
IPC分类号： H01L29/40 , H01L29/423
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/32139 , H01L21/823437 , H01L21/823468 , Y10S438/942 , Y10S438/947
摘要： A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.
摘要翻译：一种形成半导体器件的方法，包括在半导体层上形成电介质材料层，在电介质材料层上形成栅电极材料层，在栅电极材料层上形成掩模特征，在栅电极材料层的侧壁上形成间隔层掩模特征，并且在掩模特征之间的栅电极材料层上，在掩模特征之间从栅电极材料层移除间隔层，并使用硬掩模特征作为蚀刻掩模蚀刻栅电极材料层和电介质材料层，获得栅电极结构。一种半导体器件，包括第一和第二栅极电极结构，每个覆盖层包括掩模材料，该掩模材料在其侧壁处被不同于掩模材料的隔离材料包围，并且第一和第二电极结构之间的距离最多为 100nm。

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