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1. 发明申请

US20150145580A1 APPARATUS FOR CONTROLLING SEMICONDUCTOR CHIP CHARACTERISTICS 审中-公开
标题翻译：控制半导体芯片特性的装置
公开(公告)号：US20150145580A1
公开(公告)日：2015-05-28
申请号：US12346633
申请日：2008-12-30
申请人： Godfrey P. D'Souza , Keith Klayman
发明人： Godfrey P. D'Souza , Keith Klayman
IPC分类号： G06F11/30 , H03K5/05 , H03K5/07
CPC分类号： H03K5/05 , G06F11/348 , H03K5/07 , H03K2005/00019
摘要： Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.
摘要翻译：包括限定在半导体芯片上的电路的功能部件的功能部件，功能部件包括具有可修改的工作特性的部件，性能测量电路，提供指示在电路运行期间在半导体芯片上定义的电路的工作特性的输出，以及计算机实现的软件装置，用于响应于由性能测量电路提供的输出来控制具有可修改的操作特性的部件的操作特性的值。

2. 发明授权

US08566627B2 Adaptive power control 有权
公开(公告)号：US08566627B2
公开(公告)日：2013-10-22
申请号：US12502685
申请日：2009-07-14
申请人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
发明人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
IPC分类号： G06F1/00 , H03L7/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

3. 发明授权

US08405418B1 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US08405418B1
公开(公告)日：2013-03-26
申请号：US13107899
申请日：2011-05-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

4. 发明申请

US20120246453A1 METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR 有权
标题翻译：用于增强高级微处理器调度的方法和装置
公开(公告)号：US20120246453A1
公开(公告)日：2012-09-27
申请号：US13488138
申请日：2012-06-04
申请人： Guillermo J. Rozas , Godfrey P. D'Souza , Charles R. Price , Paul S. Serris
发明人： Guillermo J. Rozas , Godfrey P. D'Souza , Charles R. Price , Paul S. Serris
IPC分类号： G06F9/38
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
摘要翻译：用于使调度器软件产生代码的装置和方法，所述代码通过忽略放置在其调度操作上的一些正常约束并且简单地调度某些指令以尽可能快地运行来更快地执行，如果调度违反调度约束，则引发异常，以及确定要正确执行引发异常的每组指令的步骤。

5. 发明授权

US08209517B1 Method and apparatus for enhancing scheduling in an advanced microprocessor 有权
标题翻译：用于增强高级微处理器中的调度的方法和装置
公开(公告)号：US08209517B1
公开(公告)日：2012-06-26
申请号：US10783473
申请日：2004-02-20
申请人： Guillermo J. Rozas , Godfrey P. D'Souza , Charles R. Price , Paul S. Serris
发明人： Guillermo J. Rozas , Godfrey P. D'Souza , Charles R. Price , Paul S. Serris
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
摘要翻译：用于使调度器软件产生代码的装置和方法，所述代码通过忽略放置在其调度操作上的一些正常约束并且简单地调度某些指令以尽可能快地运行来更快地执行，如果调度违反调度约束，则引发异常，以及确定要正确执行引发异常的每组指令的步骤。

6. 发明授权

US07472033B1 Apparatus for controlling semiconductor chip characteristics 有权
标题翻译：用于控制半导体芯片特性的装置
公开(公告)号：US07472033B1
公开(公告)日：2008-12-30
申请号：US10273681
申请日：2002-10-17
申请人： Godfrey P. D'Souza , Keith Klayman
发明人： Godfrey P. D'Souza , Keith Klayman
IPC分类号： G06F11/30 , G06F9/00
CPC分类号： H03K5/05 , G06F11/348 , H03K5/07 , H03K2005/00019
摘要： Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.
摘要翻译：包括限定在半导体芯片上的电路的功能部件的功能部件，功能部件包括具有可修改的工作特性的部件，性能测量电路，提供指示在电路运行期间在半导体芯片上定义的电路的工作特性的输出，以及计算机实现的软件装置，用于响应于由性能测量电路提供的输出来控制具有可修改的操作特性的部件的操作特性的值。

7. 发明授权

US06011908A Gated store buffer for an advanced microprocessor 失效
标题翻译：高级微处理器的门控存储缓冲区
公开(公告)号：US06011908A
公开(公告)日：2000-01-04
申请号：US772686
申请日：1996-12-23
申请人： Malcolm J. Wing , Godfrey P. D'Souza
发明人： Malcolm J. Wing , Godfrey P. D'Souza
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F11/00
CPC分类号： G06F9/3808 , G06F9/3834 , G06F9/3861
摘要： A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory stores sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicating which memory stores to identical memory addresses are most recent in response to a memory access at the memory address, and circuitry for eliminating memory stores sequentially generated during a translation interval if the translation executes without generating an exception.
摘要翻译：门控存储缓冲器，包括用于临时保持与其他存储器分开的电路，用于存储在翻译间隔期间由主处理器顺序产生的所有存储器存储器，所述存储器存储器将目标指令序列转换为主机指令，用于传送在翻译间隔期间顺序生成的存储器存储器的存如果转换执行而不产生异常，则用于指示哪个存储器存储到相同的存储器地址的电路响应于存储器地址处的存储器访问是最新的，以及用于消除在转换间隔期间顺序生成的存储器存储器的电路，如果转换执行而没有产生异常。

8. 发明授权

US5546022A Static logic circuit with improved output signal levels 失效
标题翻译：具有改善输出信号电平的静态逻辑电路
公开(公告)号：US5546022A
公开(公告)日：1996-08-13
申请号：US357447
申请日：1994-12-16
申请人： Godfrey P. D'Souza , Douglas A. Laird
发明人： Godfrey P. D'Souza , Douglas A. Laird
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/00361
摘要： A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.
摘要翻译：具有改进的输出信号电平的静态逻辑电路包括具有信号节点和上拉和下拉放大器的静态互补MOSFET电路，每个具有至少一个与其相连的偏置电路。上拉和下拉放大器分别连接到VDD和VSS，并接收一个或多个逻辑信号（例如一个用于逆变器，更多用于逻辑门如AND，OR等）和一个或多个偏置信号并分别向信号节点提供上拉和下拉电压。根据施加的上拉或下拉电压，信号节点分别充电到相关节点电压大约等于VDD或VSS的充电状态。每个偏置电路接收与其相关联的上拉或下拉放大器相同的输入逻辑信号，并分别向其提供大约等于VSS或VDD的偏置信号。根据其输入逻辑信号，每个上拉或下拉放大器及其相关的偏置电路在信号节点和VDD或VSS之间提供有效电流路径，以施加所需的上拉或下拉电压，或者分别在VDD和VSS之间的漏电流路径，以分别在施加期望的上拉或下拉电压期间防止施加不期望的下拉或上拉电压。

9. 发明申请

US20130132749A1 ADAPTIVE POWER CONTROL 有权
标题翻译：自适应功率控制
公开(公告)号：US20130132749A1
公开(公告)日：2013-05-23
申请号：US13725901
申请日：2012-12-21
申请人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
发明人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
摘要翻译：一种用于控制计算机使用的功率的方法，包括以下步骤：测量计算机的中央处理器的操作特性，确定中央处理器的操作特性何时与正在进行的操作所要求的显着不同，以及改变操作中央处理器的特性与正在进行的操作相当。

10. 发明授权

US07944236B2 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US07944236B2
公开(公告)日：2011-05-17
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

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