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1. 发明申请

US20090077279A1 GENERAL PURPOSE INPUT/OUTPUT SYSTEM AND METHOD 有权
标题翻译：一般用途输入/输出系统和方法
公开(公告)号：US20090077279A1
公开(公告)日：2009-03-19
申请号：US11855761
申请日：2007-09-14
申请人： Jason Golbus , Colin N. Murphy , Alexander D. Taylor
发明人： Jason Golbus , Colin N. Murphy , Alexander D. Taylor
IPC分类号： G06F3/038 , G06F13/20 , H03M13/05
CPC分类号： H03K19/018507 , H03K19/018557 , H03K19/018585 , H04L25/0278
摘要： A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).
摘要翻译：一种用于通用输入输出（IO）的系统，包括第一焊盘; 包括所述第一垫的IO缓冲器; 以及可操作地连接到IO缓冲器的IO数据路径逻辑块，其中IO数据路径逻辑块和IO缓冲器与异构可配置集成电路（HCIC）中的通用IO块相关联。

2. 发明授权

US4639899A Memory circuit having a memory reset and recovery controller 失效
标题翻译：存储器电路具有存储器复位和恢复控制器
公开(公告)号：US4639899A
公开(公告)日：1987-01-27
申请号：US536920
申请日：1983-09-27
申请人： Colin N. Murphy , Guey T. Lu
发明人： Colin N. Murphy , Guey T. Lu
IPC分类号： G11C7/00 , G11C7/20 , G11C7/22 , G11C11/40
CPC分类号： G11C7/22 , G11C7/20
摘要： A memory circuit for storing data words including a core memory having a matrix of rows and columns of core cells which store bits of the data words, a row address decoder circuit for driving the rows, and a control signal generator, operative over one reset period and one recovery period, for controlling the columns and the row address decoder circuit to simultaneously charge the contents of the entire core memory to one data state.
摘要翻译：一种存储电路，用于存储数据字，该数据字包括具有存储数据字位的核心单元的行和列的矩阵的核心存储器，用于驱动行的行地址解码器电路，以及控制信号发生器，其在一个复位周期和一个恢复周期，用于控制列和行地址解码器电路，以将整个核心存储器的内容同时充电到一个数据状态。

3. 发明申请

US20090072858A1 HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：异构可配置集成电路
公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

4. 发明授权

US07944236B2 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US07944236B2
公开(公告)日：2011-05-17
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

5. 发明授权

US07557605B2 Heterogeneous configurable integrated circuit 有权
标题翻译：异构可配置集成电路
公开(公告)号：US07557605B2
公开(公告)日：2009-07-07
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

6. 发明授权

US08405418B1 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US08405418B1
公开(公告)日：2013-03-26
申请号：US13107899
申请日：2011-05-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

7. 发明授权

US4723108A Reference circuit 失效
标题翻译：参考电路
公开(公告)号：US4723108A
公开(公告)日：1988-02-02
申请号：US886835
申请日：1986-07-16
申请人： Colin N. Murphy , Robert G. Pugh
发明人： Colin N. Murphy , Robert G. Pugh
IPC分类号： G05F1/46 , G05F3/24 , G05F3/26
CPC分类号： G05F1/463 , G05F3/245
摘要： A reference circuit for compensating for the natural response of MOS circuits to changes in temperature and manufacturing variances. The reference circuit comprises a voltage reference circuit that generates a stable current over variations of temperature and includes a current mirror circuit coupled to a first MOS transistor which is biased so that its change in threshold voltage due to temperature variations is compensated by its change in transconductance due to temperature variations, which voltage reference circuit produces a stable current through a second MOS transistor, which stable current is applied to a voltage generator circuit which modulates the gate bias voltage of a third MOS transistor such that the gate to source bias of the third MOS transistor is varied to compensate for variations in temperature.
摘要翻译：用于补偿MOS电路对温度变化和制造方差的自然响应的参考电路。参考电路包括电压参考电路，其在温度变化时产生稳定的电流，并且包括耦合到第一MOS晶体管的电流镜电路，该第一MOS晶体管被偏置，使得由于温度变化而导致的阈值电压的变化由其跨导的变化来补偿由于温度变化，哪个电压参考电路产生通过第二MOS晶体管的稳定电流，该稳定电流被施加到电压发生器电路，该电压发生器电路调制第三MOS晶体管的栅极偏置电压，使得第三改变MOS晶体管以补偿温度变化。

8. 发明授权

US08049531B2 General purpose input/output system and method 有权
标题翻译：通用输入/输出系统及方法
公开(公告)号：US08049531B2
公开(公告)日：2011-11-01
申请号：US11855761
申请日：2007-09-14
申请人： Jason Golbus , Colin N. Murphy , Alexander D. Taylor
发明人： Jason Golbus , Colin N. Murphy , Alexander D. Taylor
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/018507 , H03K19/018557 , H03K19/018585 , H04L25/0278
摘要： A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).
摘要翻译：一种用于通用输入输出（IO）的系统，包括第一焊盘; 包括所述第一垫的IO缓冲器; 以及可操作地连接到IO缓冲器的IO数据路径逻辑块，其中IO数据路径逻辑块和IO缓冲器与异构可配置集成电路（HCIC）中的通用IO块相关联。

9. 发明授权

US07902862B2 High-bandwidth interconnect network for an integrated circuit 有权
标题翻译：用于集成电路的高带宽互连网络
公开(公告)号：US07902862B2
公开(公告)日：2011-03-08
申请号：US11901182
申请日：2007-09-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

10. 发明申请

US20100306429A1 System and Method of Signal Processing Engines With Programmable Logic Fabric 有权
标题翻译：信号处理引擎与可编程逻辑结构的系统与方法
公开(公告)号：US20100306429A1
公开(公告)日：2010-12-02
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

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