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1. 发明授权

US07944236B2 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US07944236B2
公开(公告)日：2011-05-17
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

2. 发明授权

US08405418B1 High-bandwidth interconnect network for an integrated circuit 有权
公开(公告)号：US08405418B1
公开(公告)日：2013-03-26
申请号：US13107899
申请日：2011-05-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

3. 发明授权

US07902862B2 High-bandwidth interconnect network for an integrated circuit 有权
标题翻译：用于集成电路的高带宽互连网络
公开(公告)号：US07902862B2
公开(公告)日：2011-03-08
申请号：US11901182
申请日：2007-09-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H03K19/173
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

4. 发明申请

US20100306429A1 System and Method of Signal Processing Engines With Programmable Logic Fabric 有权
标题翻译：信号处理引擎与可编程逻辑结构的系统与方法
公开(公告)号：US20100306429A1
公开(公告)日：2010-12-02
申请号：US12855466
申请日：2010-08-12
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

5. 发明申请

US20090073967A1 High-bandwidth interconnect network for an integrated circuit 有权
标题翻译：用于集成电路的高带宽互连网络
公开(公告)号：US20090073967A1
公开(公告)日：2009-03-19
申请号：US11901182
申请日：2007-09-14
申请人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
发明人： Dana How , Godfrey P. D'Souza , Malcolm J. Wing , Colin N. Murphy , Arun Jangity
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
摘要翻译：总线结构在逻辑电路和集成电路的专用电路之间提供流水线传输数据，总线结构包括流水线导体网络，并且连接器选择性地将流水线导体连接在专用电路，其它流水线连接器和逻辑电路。

6. 发明申请

US20090072858A1 HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：异构可配置集成电路
公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

7. 发明授权

US07557605B2 Heterogeneous configurable integrated circuit 有权
标题翻译：异构可配置集成电路
公开(公告)号：US07557605B2
公开(公告)日：2009-07-07
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译：一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速网状互连结构被配置为实现横跨系统的多个互连管线总线。

8. 发明授权

US06011908A Gated store buffer for an advanced microprocessor 失效
标题翻译：高级微处理器的门控存储缓冲区
公开(公告)号：US06011908A
公开(公告)日：2000-01-04
申请号：US772686
申请日：1996-12-23
申请人： Malcolm J. Wing , Godfrey P. D'Souza
发明人： Malcolm J. Wing , Godfrey P. D'Souza
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F11/00
CPC分类号： G06F9/3808 , G06F9/3834 , G06F9/3861
摘要： A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory stores sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicating which memory stores to identical memory addresses are most recent in response to a memory access at the memory address, and circuitry for eliminating memory stores sequentially generated during a translation interval if the translation executes without generating an exception.
摘要翻译：门控存储缓冲器，包括用于临时保持与其他存储器分开的电路，用于存储在翻译间隔期间由主处理器顺序产生的所有存储器存储器，所述存储器存储器将目标指令序列转换为主机指令，用于传送在翻译间隔期间顺序生成的存储器存储器的存如果转换执行而不产生异常，则用于指示哪个存储器存储到相同的存储器地址的电路响应于存储器地址处的存储器访问是最新的，以及用于消除在转换间隔期间顺序生成的存储器存储器的电路，如果转换执行而没有产生异常。

9. 发明授权

US08824468B2 System and method for parsing frames 有权
标题翻译：用于解析帧的系统和方法
公开(公告)号：US08824468B2
公开(公告)日：2014-09-02
申请号：US13226195
申请日：2011-09-06
申请人： Malcolm J. Wing , Jay B. Patel , Jeffrey M. Schroeder
发明人： Malcolm J. Wing , Jay B. Patel , Jeffrey M. Schroeder
IPC分类号： H04L12/28 , H04L12/26 , H04L29/06 , H04L29/08 , H04J1/16
CPC分类号： H04L43/18 , H04L69/12 , H04L69/22 , H04L69/324
摘要： A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.
摘要翻译：一种用于解析帧的系统，包括被配置为从第一帧识别第一小区的第一小区提取电路（CEC），可操作地连接到第一CEC的第一解析器引擎，其中第一解析器引擎被配置为基于第一单元和第一转发电路，其可操作地连接到第一解析器引擎并且被配置为转发结果，其中第一CEC，第一解析器引擎和第一转发电路与第一帧解析器单元相关联。

10. 发明申请

US20110317720A1 System and Method for Parsing Frames 有权
标题翻译：分析框架的系统和方法
公开(公告)号：US20110317720A1
公开(公告)日：2011-12-29
申请号：US13226195
申请日：2011-09-06
申请人： Malcolm J. Wing , Jay B. Patel , Jeffrey M. Schroeder
发明人： Malcolm J. Wing , Jay B. Patel , Jeffrey M. Schroeder
IPC分类号： H04J99/00
CPC分类号： H04L43/18 , H04L69/12 , H04L69/22 , H04L69/324
摘要： A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.
摘要翻译：一种用于解析帧的系统，包括被配置为从第一帧识别第一小区的第一小区提取电路（CEC），可操作地连接到第一CEC的第一解析器引擎，其中第一解析器引擎被配置为基于第一单元和第一转发电路，其可操作地连接到第一解析器引擎并且被配置为转发结果，其中第一CEC，第一解析器引擎和第一转发电路与第一帧解析器单元相关联。

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