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1. 发明申请

US20130033295A1 CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS 有权
标题翻译：调节电压电路的时钟相位补偿
公开(公告)号：US20130033295A1
公开(公告)日：2013-02-07
申请号：US13195020
申请日：2011-08-01
申请人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
发明人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.
摘要翻译：调整双时钟树中时钟信号的时钟相位，以补偿时钟树中缓冲区的传播延迟的变化。产生第一输入时钟和第二输入时钟，第二输入时钟具有例如当系统在降低的工作电压或不同温度下操作时相对于第一输入时钟可编程地移位的相位。第一和第二输入时钟耦合到双重时钟触发器，每个具有主锁存器和次锁存器。响应于第一输入时钟和第二输入时钟产生复合时钟信号。例如，响应于复合时钟信号，第一信号被锁存在主锁存器中，并且响应于第一输入时钟信号将第二信号锁存在次锁存器中。

2. 发明申请

US20100103760A1 Memory Power Management Systems and Methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US20100103760A1
公开(公告)日：2010-04-29
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

3. 发明授权

US06903780B2 Method of expanding high-speed serial video data providing compatibility with a class of DVI receivers 有权
标题翻译：扩展与一类DVI接收机兼容的高速串行视频数据的方法
公开(公告)号：US06903780B2
公开(公告)日：2005-06-07
申请号：US09966167
申请日：2001-09-28
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： G09G5/00 , H03M7/30 , H04L25/49 , H04N7/24 , H04N7/26 , H04N7/04
CPC分类号： G09G5/006 , H03M7/30 , H04L25/4908 , H04N7/24 , H04N19/184
摘要： A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio data, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data.
摘要翻译：一种将数据扩展到高速串行视频链路的方式，使得现有接收机不可见，并且可以传输辅助数据（即，音频数据），而无需了解显示器的能力来接收辅助信号数据。

4. 发明授权

US07630270B2 Dual mode SRAM architecture for voltage scaling and power management 有权
标题翻译：用于电压缩放和电源管理的双模式SRAM架构
公开(公告)号：US07630270B2
公开(公告)日：2009-12-08
申请号：US11841310
申请日：2007-08-20
申请人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
发明人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C11/413
摘要： The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.
摘要翻译：本公开提供了一种双模电压控制器，向SRAM外围电路提供电压的方法和集成电路。在一个实施例中，双模式电压控制器用于与SRAM阵列一起使用，并且包括连接到数字核心电压和SRAM阵列电压的电压切换单元，以形成能够在数字电源之间切换至少一个SRAM外围电路的结构核心电压和SRAM阵列电压。

5. 发明申请

US20080043560A1 DUAL MODE SRAM ARCHITECTURE FOR VOLTAGE SCALING AND POWER MANAGEMENT 有权
标题翻译：用于电压调节和电源管理的双模SRAM架构
公开(公告)号：US20080043560A1
公开(公告)日：2008-02-21
申请号：US11841310
申请日：2007-08-20
申请人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
发明人： Uming Ko , Gordon Gammie , Sumanth K. Gururajarao
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C7/02 , G11C11/413
摘要： The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.
摘要翻译：本公开提供了一种双模电压控制器，向SRAM外围电路提供电压的方法和集成电路。在一个实施例中，双模式电压控制器用于与SRAM阵列一起使用，并且包括连接到数字核心电压和SRAM阵列电压的电压切换单元，以形成能够在数字电路之间切换至少一个SRAM外围电路的结构核心电压和SRAM阵列电压。

6. 发明申请

US20050194592A1 Adaptive voltage control for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制
公开(公告)号：US20050194592A1
公开(公告)日：2005-09-08
申请号：US11045222
申请日：2005-01-28
申请人： Hugh Mair , Gordon Gammie , Alice Wang
发明人： Hugh Mair , Gordon Gammie , Alice Wang
IPC分类号： H01L29/04
CPC分类号： G11C5/147
摘要： A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.
摘要翻译：一种用于自适应地控制提供给基本上靠近设备的电路的电压的装置，包括处理模块，耦合到处理模块的第一跟踪元件，并产生指示与电路相关联的第一估计速度的第一值，以及第二跟踪元件耦合到所述处理模块并产生指示与所述电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与目标值进行比较，并且基于所述比较使电压输出被调整。

7. 发明授权

US06633243B2 Method of encoding video data for serial transmission 有权
标题翻译：编码串行传输的视频数据的方法
公开(公告)号：US06633243B2
公开(公告)日：2003-10-14
申请号：US09953803
申请日：2001-09-17
申请人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
发明人： Hugh Mair , Gordon Gammie , Steve Clynes , Rolf Lagerquist
IPC分类号： H03M700
CPC分类号： G09G5/006 , H03M7/14 , H04L25/4908 , H04N19/184
摘要： An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a ‘1’ for the purpose of removing ‘rogue’ character sequences; otherwise it is always set to a ‘0’.
摘要翻译：编码方案简化了DVI 1.0规范中描述的TMDS编码算法，同时保留了与大多数现有DVI接收器的兼容性。过渡控制位的生成已被删除; 虽然INV位具有与DVI 1.0标准中的DC位相似的功能，但是用于推导它的算法是非常不同的。不要在电缆上维持直流平衡。相反，为了消除“流氓”字符序列，将INV位设置为“1” 否则始终设置为“0”。

8. 发明授权

US08564351B2 Clock phase compensation for adjusted voltage circuits 有权
标题翻译：调整后的电压电路的时钟相位补偿
公开(公告)号：US08564351B2
公开(公告)日：2013-10-22
申请号：US13195020
申请日：2011-08-01
申请人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
发明人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.
摘要翻译：调整双时钟树中时钟信号的时钟相位，以补偿时钟树中缓冲区的传播延迟的变化。产生第一输入时钟和第二输入时钟，第二输入时钟具有例如当系统在降低的工作电压或不同温度下操作时相对于第一输入时钟可编程地移位的相位。第一和第二输入时钟耦合到双重时钟触发器，每个具有主锁存器和次锁存器。响应于第一输入时钟和第二输入时钟产生复合时钟信号。例如，响应于复合时钟信号，第一信号被锁存在主锁存器中，并且响应于第一输入时钟信号将第二信号锁存在次锁存器中。

9. 发明授权

US08302047B2 Statistical static timing analysis in non-linear regions 有权
标题翻译：非线性区域的统计静态时序分析
公开(公告)号：US08302047B2
公开(公告)日：2012-10-30
申请号：US12766643
申请日：2010-04-23
申请人： Dennis Darcy Buss , Alice Wang , Gordon Gammie , Jle Gu , Rahul Jagdish Rithe , Satyendra R. P. Raju Datla , Sharon Hsiao-Wei Chou
发明人： Dennis Darcy Buss , Alice Wang , Gordon Gammie , Jle Gu , Rahul Jagdish Rithe , Satyendra R. P. Raju Datla , Sharon Hsiao-Wei Chou
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： H03G9/025 , G10L19/00 , H03G7/007 , H03G9/00 , H03G9/005
摘要： A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.
摘要翻译：描述了当本地晶体管变化确定随机延迟时模拟集成电路设计的f-sigma定时路径延迟的方法。这通过使用局部变化（NLOPALV）的非线性工作点分析来确定第一定时路径的估计延迟时间来实现。为集成电路设计中的定时路径中包含的每个单元计算工作点。电池弧的f-σ工作点是电池电弧延迟功能（CADF）上的一个点。使用小区的CADF上的所选择的操作点为每个小区确定f-sigma延迟值。然后可以将定时路径中的多个小区的确定的延迟值组合以预测整个定时路径的估计延迟。该方法可以扩展以处理压摆率，预测保持时间统计，修剪路径和处理收敛路径。

10. 发明申请

US20110216619A1 MEMORY POWER MANAGEMENT SYSTEMS AND METHODS 审中-公开
标题翻译：存储电源管理系统和方法
公开(公告)号：US20110216619A1
公开(公告)日：2011-09-08
申请号：US13106612
申请日：2011-05-12
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

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