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1. 发明授权

US08051313B2 Apparatus, system and method of power state control 有权
标题翻译：电力状态控制的装置，系统和方法
公开(公告)号：US08051313B2
公开(公告)日：2011-11-01
申请号：US12110589
申请日：2008-04-28
申请人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
发明人： Bixia Li , Hugh Mair , Minh Chau , Alice Wang , Uming Ko
IPC分类号： G06F1/00 , G05F1/10 , H03K3/02 , H03K17/16
CPC分类号： H03K3/0375
摘要： An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
摘要翻译：用于在电力域中异步降低功率的装置，系统和方法。在一个实施例中，该方法包括：（1）接收功率域的睡眠命令，（2）在接收到睡眠命令时接收表示功率域中的保留区域已存储数据的肯定保持状态信号（ 3）在接收到睡眠命令时接收表示已经发生功率域隔离的肯定隔离状态信号，以及（4）至少在接收到睡眠命令时向功率域提供功率域关闭命令，肯定的状态保持信号和肯定状态隔离信号。在另一个实施例中，采用多个使能信号来产生功率开关的“无毛刺”控制。

2. 发明授权

US07660150B2 Memory cell having improved write stability 有权
标题翻译：具有改善的写入稳定性的存储单元
公开(公告)号：US07660150B2
公开(公告)日：2010-02-09
申请号：US11967472
申请日：2007-12-31
申请人： Donald George Mikan, Jr. , Hugh Mair
发明人： Donald George Mikan, Jr. , Hugh Mair
IPC分类号： G11C11/40
CPC分类号： G11C11/419 , G11C11/412
摘要： A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.
摘要翻译：提供了一种用于向具有与写访问电路分离和隔离的读访问电路的存储单元进行写入的方法。该方法包括提供逻辑状态，以通过写入存取电路将写入存储单元的逻辑状态写入耦合到存储单元的写入位线，将写入存取电路的控制从禁用的低电压状态改变为激活的写入字线将读取访问电路从激活的低电压状态改变为去激活的高电压状态，其中读取字线上的电压变化为写入字上的电压提供电压升高由读取字线和写入字线之间的电耦合引起的线，以在写入操作期间向存储器单元提供写入辅助。

3. 发明授权

US07633314B2 System and method for reducing power-on-transient current magnitude 有权
标题翻译：用于降低功率瞬态电流幅度的系统和方法
公开(公告)号：US07633314B2
公开(公告)日：2009-12-15
申请号：US11563868
申请日：2006-11-28
申请人： Hugh Mair , Rolf Lagerquist
发明人： Hugh Mair , Rolf Lagerquist
IPC分类号： H03K19/096
CPC分类号： H03K17/164
摘要： System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要翻译：用于降低分布式报头交换机上的上电瞬态电流幅度的系统和方法。优选实施例包括将电路耦合到电源的分布式头部开关，分配的头部开关包括线性顺序的组合开关，每个组合开关包含预充电开关和头部开关。一次通过涉及顺序打开每个预充电开关，这使得分配的标头开关处的电压电平接近最终电压电平的电压电平，而第二次通过涉及顺序地接通每个标头开关。由于分布式标题开关处的电压电平接近最终的电压电平，所以产生的瞬态电流的幅度很小。

4. 发明申请

US20060123074A1 Representing Data Having Multi-dimensional Input Vectors and Corresponding Output Element by Piece-wise Polynomials 有权
标题翻译：表示具有多维输入向量的数据和通过分段多项式的相应输出元素
公开(公告)号：US20060123074A1
公开(公告)日：2006-06-08
申请号：US10904973
申请日：2004-12-07
申请人： Girishankar GURUMURTHY , Shitanshu TIWARI , Hugh MAIR , Sumanth GURURAJARAO
发明人： Girishankar GURUMURTHY , Shitanshu TIWARI , Hugh MAIR , Sumanth GURURAJARAO
IPC分类号： G06F1/02
CPC分类号： G06F17/175
摘要： determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.
摘要翻译：确定分段多项式，它们一起将表示具有多维输入向量和对应的输出元素的大数据集。在一个实施例中，函数/过程/例程被递归地调用/调用以确定分段多项式是数据集不能被一个多项式完全建模。本发明的另一方面减少了在确定多项式时要尝试的满足各种精度要求的组合（形成多项式的子多项式的顺序）的数量。基于这样的认识可以获得这样的减少：当一维中的顺序增加并且结果不会导致多项式的可接受的精度时，可以排除具有较小数量（对于维度）的组合，。

5. 发明申请

US20060087361A1 Methods and apparatus to bias the backgate of a power switch 有权
标题翻译：偏置电源开关背栅的方法和装置
公开(公告)号：US20060087361A1
公开(公告)日：2006-04-27
申请号：US10970601
申请日：2004-10-21
申请人： Shanthi Bhagavatheeswaran , Srinivasan Venkatraman , Hugh Mair
发明人： Shanthi Bhagavatheeswaran , Srinivasan Venkatraman , Hugh Mair
IPC分类号： H03K17/687
CPC分类号： H03K17/693 , H03K17/162
摘要： Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.
摘要翻译：公开了在防止闩锁的同时偏置电源开关的背栅的方法和装置。所公开的偏置电源开关的背栅的方法包括：如果第一电源的电压在第二电源的电压之前上升，则基于第一电源以最初的电压偏压背栅; 并且如果第一电源的电压在第二电源的电压之后上升，则以基于第二电源的电压偏压背栅。

6. 发明申请

US20050189972A1 System and method for achieving low power standby and fast relock for digital phase lock loop 审中-公开
标题翻译：实现数字锁相环的低功耗待机和快速重锁的系统和方法
公开(公告)号：US20050189972A1
公开(公告)日：2005-09-01
申请号：US10788709
申请日：2004-02-27
申请人： Tim Foo , Baher Haroun , Hugh Mair
发明人： Tim Foo , Baher Haroun , Hugh Mair
IPC分类号： H03L7/06 , H03L7/08 , H03L7/099
CPC分类号： H03L7/0802 , H03L7/0991
摘要： A digital phase lock loop (DPLL) system and method employ digital loop control and a digital controller to drive the DPLL oscillator with fast re-lock capability. The DPLL optionally uses low power retention flops to implement low power and fast interrupt services.
摘要翻译：数字锁相环（DPLL）系统和方法采用数字环路控制和数字控制器，以快速重新锁定功能驱动DPLL振荡器。 DPLL可选择使用低功耗保护触发器来实现低功耗和快速中断服务。

7. 发明授权

US06570415B2 Reduced voltage swing digital differential driver 有权
公开(公告)号：US06570415B2
公开(公告)日：2003-05-27
申请号：US10158659
申请日：2002-05-30
申请人： Hao Chen , Rolf Lagerquist , Hugh Mair
发明人： Hao Chen , Rolf Lagerquist , Hugh Mair
IPC分类号： H03B100
CPC分类号： H04L25/0272 , H03K17/04106 , H03K17/04123 , H03K19/0013 , H03K2217/0036 , H04L25/028
摘要： A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

8. 发明授权

US08812885B2 Detecting wake-up events for a chip based on an I/O power supply 有权
标题翻译：基于I / O电源检测芯片的唤醒事件
公开(公告)号：US08812885B2
公开(公告)日：2014-08-19
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

9. 发明申请

US20140016718A1 REDUCTION IN POWER SUPPLY INDUCED JITTER ON A SERDES TRANSMITTER 有权
标题翻译：电源发射机上电源诱发抖动的减少
公开(公告)号：US20140016718A1
公开(公告)日：2014-01-16
申请号：US13546635
申请日：2012-07-11
申请人： Vishnu Ravinuthula , Dushmantha Rajapaksha , Hugh Mair
发明人： Vishnu Ravinuthula , Dushmantha Rajapaksha , Hugh Mair
IPC分类号： H04B1/04
CPC分类号： H03L7/18
摘要： In an embodiment of the invention, a frequency divider in a PLL (phase-locked loop) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first DC (direct current) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.
摘要翻译：在本发明的一个实施例中，PLL（锁相环）电路中的分频器由电源提供给发送电路的电源。 PLL被配置为接收第一DC（直流）参考电压，第二DC电压和参考时钟信号。 PLL被配置为产生传输时钟信号。发送电路被配置为接收传输时钟信号，第二DC电压和数据总线，其中数据总线并行包括多个数据位。传输电路串行传输数据。

10. 发明申请

US20080162969A1 DETECTING WAKE-UP EVENTS FOR A CHIP BASED ON AN I/O POWER SUPPLY 有权
标题翻译：检测基于I / O电源的芯片的唤醒事件
公开(公告)号：US20080162969A1
公开(公告)日：2008-07-03
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

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