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1. 发明申请

US20110261629A1 Reduced Power Consumption in Retain-Till-Accessed Static Memories 有权
标题翻译：在保留直通静态存储器中降低功耗
公开(公告)号：US20110261629A1
公开(公告)日：2011-10-27
申请号：US12764369
申请日：2010-04-21
申请人： Anand Seshadri , Hugh Thomas Mair
发明人： Anand Seshadri , Hugh Thomas Mair
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells.
摘要翻译：具有保留直到访问（RTA）模式的静态随机存取存储器（SRAM）的偏置电路。存储器由多个存储器阵列块构成，每个存储器阵列块包括由阵列晶体管形成的SRAM单元; 阵列之外的功能和其它电路由与晶体管不同的构造的核心晶体管形成。偏置器件包括在每个存储器阵列块内，偏置器件被构造为一个或多个阵列晶体管。用于存储器阵列块的偏置装置可以彼此并联连接。在RTA模式下，偏置器件会降低每个SRAM单元的电源电压差。在正常工作模式下，核心晶体管用作开关，使偏置器件短路，从而在整个SRAM单元上出现全部电源差分。

2. 发明申请

US20090097327A1 SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY 有权
标题翻译：用于从存储阵列读取数据的系统和方法
公开(公告)号：US20090097327A1
公开(公告)日：2009-04-16
申请号：US12337946
申请日：2008-12-18
申请人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
发明人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/12 , G11C11/419
摘要： One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.
摘要翻译：本发明的一个实施例包括用于从存储器阵列访问数据的列多路复用器，所述存储器阵列包括具有基于控制节点的逻辑状态的逻辑状态的输出节点和列元素，每个列元素包括第一对串联连接的开关由列选择信号和与存储在多个存储单元中的数据相关联的位线信号控制。第一对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑低电平状态。列元件每个还包括由位线信号和列选择信号的补码控制的第二对串联连接开关。第二对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑高状态。

3. 发明授权

US07474582B2 Systems and methods for managing power 有权
标题翻译：管理电源的系统和方法
公开(公告)号：US07474582B2
公开(公告)日：2009-01-06
申请号：US11637352
申请日：2006-12-12
申请人： Hugh Thomas Mair , James Sangwon Song , Franck Benjamin Dahan , William Douglas Wilson , Norman LeRoy Culp , Sudha Thiruvengadam
发明人： Hugh Thomas Mair , James Sangwon Song , Franck Benjamin Dahan , William Douglas Wilson , Norman LeRoy Culp , Sudha Thiruvengadam
IPC分类号： G11C5/14 , G11C11/00 , G11C7/06
CPC分类号： G11C5/147 , G11C5/143 , G11C2207/2227
摘要： One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.
摘要翻译：本发明的一个实施例包括用于管理存储器阵列的功率的系统。该系统包括比较器，其被配置为将第一电压与参考电压进行比较。第一电压可以对应于与存储器阵列相关联的外围电路中的至少一个的工作电压和被配置为与外围电路通信的逻辑电路。参考电压可以对应于存储器阵列的读/写操作的最小阈值电压。该系统还包括输出电路，其配置为响应于比较器的输出向存储器阵列提供输出电压。输出电压可以是外围电路和逻辑电路中的至少一个的工作电压的最大值和最小阈值电压。

4. 发明申请

US20080155282A1 Adaptive voltage scaling with age compensation 有权
标题翻译：适应电压调整与年龄补偿
公开(公告)号：US20080155282A1
公开(公告)日：2008-06-26
申请号：US11643194
申请日：2006-12-21
申请人： Gordon Gammie , Alice Wang , Hugh Thomas Mair
发明人： Gordon Gammie , Alice Wang , Hugh Thomas Mair
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.
摘要翻译：本发明的一个实施例包括与集成电路（IC）相关联的自适应电压缩放系统。该系统包括至少一个目标性能电路，其包括第一半导体材料并被配置为响应于基于所施加的电压实现目标性能来确定至少一个电压电位。该系统还包括控制器，该控制器被配置为将可变电源的输出设置为所确定的至少一个电压电位;以及老化控制器，其被配置为控制所述至少一个目标性能电路以使所述第一半导体材料以至少基本上与IC中的其它电路的寿命相当。

5. 发明申请

US20130033295A1 CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS 有权
标题翻译：调节电压电路的时钟相位补偿
公开(公告)号：US20130033295A1
公开(公告)日：2013-02-07
申请号：US13195020
申请日：2011-08-01
申请人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
发明人： Hugh Thomas Mair , Jie Gu , Gordon Gammie
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.
摘要翻译：调整双时钟树中时钟信号的时钟相位，以补偿时钟树中缓冲区的传播延迟的变化。产生第一输入时钟和第二输入时钟，第二输入时钟具有例如当系统在降低的工作电压或不同温度下操作时相对于第一输入时钟可编程地移位的相位。第一和第二输入时钟耦合到双重时钟触发器，每个具有主锁存器和次锁存器。响应于第一输入时钟和第二输入时钟产生复合时钟信号。例如，响应于复合时钟信号，第一信号被锁存在主锁存器中，并且响应于第一输入时钟信号将第二信号锁存在次锁存器中。

6. 发明授权

US08278980B1 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
公开(公告)号：US08278980B1
公开(公告)日：2012-10-02
申请号：US13484472
申请日：2012-05-31
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

7. 发明授权

US08218376B2 Reduced power consumption in retain-till-accessed static memories 有权
标题翻译：在保留直到访问的静态存储器中降低功耗
公开(公告)号：US08218376B2
公开(公告)日：2012-07-10
申请号：US12764369
申请日：2010-04-21
申请人： Anand Seshadri , Hugh Thomas Mair
发明人： Anand Seshadri , Hugh Thomas Mair
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells.
摘要翻译：具有保留直到访问（RTA）模式的静态随机存取存储器（SRAM）的偏置电路。存储器由多个存储器阵列块构成，每个存储器阵列块包括由阵列晶体管形成的SRAM单元; 阵列之外的功能和其它电路由与晶体管不同的构造的核心晶体管形成。偏置器件包括在每个存储器阵列块内，偏置器件被构造为一个或多个阵列晶体管。用于存储器阵列块的偏置装置可以彼此并联连接。在RTA模式下，偏置器件会降低每个SRAM单元的电源电压差。在正常工作模式下，核心晶体管用作开关，使偏置器件短路，从而在整个SRAM单元上出现全部电源差分。

8. 发明申请

US20110304994A1 CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING 有权
标题翻译：导电性通过布瓦多孔和低电阻的结构和制造工艺
公开(公告)号：US20110304994A1
公开(公告)日：2011-12-15
申请号：US13101760
申请日：2011-05-05
申请人： Hugh Thomas Mair
发明人： Hugh Thomas Mair
IPC分类号： H05K1/02 , H01L21/28 , H01L23/48
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/78 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.
摘要翻译：集成电路结构包括：第一导电层（MET4），包括第一分叉导电结构（310），绝缘层（320，ILD45），基本上设置在第一叉形导电结构（310）上;多个导电通孔（331- 334）通过绝缘层（ILD45）并与第一分叉导电结构（310）电连接，以及包括基本上设置在绝缘层的至少一部分上的第二分叉导电结构（340）的第二导电层（MET5）（ILD45）并且通常垂直于第一分叉导电结构（310），与第二分叉导电结构（340）电连接的多个导电通孔（331-334）。还公开了其它结构，装置和方法。

9. 发明申请

US20110037447A1 Component Powered by HDMI Interface 有权
标题翻译：组件由HDMI接口供电
公开(公告)号：US20110037447A1
公开(公告)日：2011-02-17
申请号：US12542685
申请日：2009-08-17
申请人： Hugh Thomas Mair
发明人： Hugh Thomas Mair
IPC分类号： G05F1/46
CPC分类号： G06F1/266
摘要： A HDMI (High-Definition Multimedia Interface) transmitter component may be operated solely on power that is scavenged and converted from termination tail current received while the HDMI transmitter component is coupled to an HDMI compliant sink connector on a HDMI receiver component. The termination tail current is received at the transmitter component from a plurality of differential HDMI signals from terminators on a receiver component. A portion of the received tail current is converted to form a supply voltage Vdd source. Function logic on the transmitter component is operated using the Vdd voltage, and the function logic is configured to control the plurality of differential signals.
摘要翻译： HDMI（高清晰度多媒体接口）发射器组件可以仅在HDMI接收器组件耦合到HDMI接收器组件上的HDMI兼容接收器连接器时接收到的终端尾部电流被清除和转换的电源上运行。终端尾部电流在来自接收器部件上的终端器的多个差分HDMI信号的发射器部件处被接收。接收的尾部电流的一部分被转换以形成电源电压Vdd源。使用Vdd电压来操作发射机部件上的功能逻辑，并且功能逻辑被配置为控制多个差分信号。

10. 发明申请

US20080116455A1 TECHNIQUE FOR AGING INDUCED PERFORMANCE DRIFT COMPENSATION IN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中老化诱导性能干扰补偿的技术
公开(公告)号：US20080116455A1
公开(公告)日：2008-05-22
申请号：US11562431
申请日：2006-11-22
申请人： PALKESH JAIN , Hugh Thomas Mair
发明人： PALKESH JAIN , Hugh Thomas Mair
IPC分类号： H01L23/58 , G01R31/27 , H01L27/00
CPC分类号： H03L1/00 , G01R31/2855
摘要： An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one example embodiment, this is achieved by applying a body bias voltage VBB to the integrated circuit to compensate for the lifetime performance drift due to hot carrier and NBTI induced aging
摘要翻译：一种改进的补偿电路，可补偿由于集成电路老化引起的寿命性能漂移，从而提高电路性能。在一个示例实施例中，这通过将体偏置电压VBB施加到集成电路来补偿由于热载流子和NBTI诱导的老化引起的寿命性能漂移而实现

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