专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06615337B1 Method and apparatus for maintaining coherency in a translation lookaside buffer 有权
标题翻译：用于在翻译后备缓冲器中维持一致性的方法和装置
公开(公告)号：US06615337B1
公开(公告)日：2003-09-02
申请号：US09925954
申请日：2001-08-09
申请人： Michael Clark , Michael A. Filippo , Benjamin Sander , Greg Smaus
发明人： Michael Clark , Michael A. Filippo , Benjamin Sander , Greg Smaus
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F2212/682
摘要： In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.
摘要翻译：在一个说明性实施例中，提供了一种用于控制翻译后备缓冲器的装置。该装置包括翻译单元，缓冲器和比较器。翻译单元适于发起表步骤处理以将虚拟存储器地址转换为物理地址。缓冲器适于存储先前由翻译单元处理的未决存储器访问请求。比较器适于确定由平移单元的桌面移动过程产生的物理地址是否与待处理的存储器访问请求中的至少一个的物理地址相冲突，并将控制信号传送到翻译单元以取消表格行走响应确定存在冲突的过程。

2. 发明授权

US06339808B1 Address space conversion to retain software compatibility in new architectures 有权
标题翻译：地址空间转换，以保持新体系结构中的软件兼容性
公开(公告)号：US06339808B1
公开(公告)日：2002-01-15
申请号：US09224820
申请日：1999-01-04
申请人： Larry Hewitt , Greg Smaus
发明人： Larry Hewitt , Greg Smaus
IPC分类号： G06F1324
CPC分类号： G06F13/24 , G06F13/404
摘要： A multi-processor computer system includes at least a first and second processor coupled to a host bus. The first processor accesses a first set of registers using a first plurality of addresses over the host bus. A second processor accesses a second set of registers using the first plurality of addresses over the host bus. A first integrated circuit forms a bridge between the host bus and an input/output bus. The first integrated circuit receives access requests for the first and second sets of registers from the first and second processors, respectively. A second integrated circuit, coupled to the input/output bus, includes a first and a second local interrupt controller, the first and second sets of registers being part of the first and second local interrupt controllers. The first integrated circuit, responsive to an access request from one of the processors to one of the first plurality of addresses, outputs information on the input/output bus indicating the address of the register being accessed and which of the first and second processors made the access request, thereby specifying one of the first and second sets of registers.
摘要翻译：多处理器计算机系统至少包括耦合到主机总线的第一和第二处理器。第一处理器使用主机总线上的第一多个地址访问第一组寄存器。第二处理器使用主机总线上的第一多个地址访问第二组寄存器。第一集成电路在主机总线和输入/输出总线之间形成一个桥。第一集成电路分别从第一和第二处理器接收针对第一和第二组寄存器的访问请求。耦合到输入/输出总线的第二集成电路包括第一和第二局部中断控制器，第一和第二组寄存器是第一和第二局部中断控制器的一部分。第一集成电路响应于从处理器之一到第一多个地址之一的访问请求，输出关于输入/输出总线的信息，指示正在被访问的寄存器的地址，以及第一和第二处理器中的哪一个使访问请求，从而指定第一和第二组寄存器之一。

3. 发明授权

US06253304B1 Collation of interrupt control devices 有权
标题翻译：中断控制装置的整理
公开(公告)号：US06253304B1
公开(公告)日：2001-06-26
申请号：US09224821
申请日：1999-01-04
申请人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
发明人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
IPC分类号： G06F946
CPC分类号： G06F9/4812
摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.
摘要翻译：第一和第二局部中断控制器设置在单个集成电路上。第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式