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1. 发明申请

US20080256338A1 Techniques for Storing Instructions and Related Information in a Memory Hierarchy 有权
标题翻译：在内存层次结构中存储指令和相关信息的技术
公开(公告)号：US20080256338A1
公开(公告)日：2008-10-16
申请号：US11735567
申请日：2007-04-16
申请人： David Neal Suggs
发明人： David Neal Suggs
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/30152 , G06F9/30156 , G06F9/3017 , G06F9/30178 , G06F9/3806 , G06F9/382 , G06F9/3844
摘要： A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory.
摘要翻译：存储器子系统包括第一存储器，第二存储器，第一压缩器和第一解压缩器。第一存储器被配置为存储取出窗口的指令字节，并且存储表征提取窗口的指令字节的第一预解码信息和第一分支信息。第二存储器被配置为在从第一存储器消除指令字节并存储也表征获取窗口的指令字节的组合预解码/转移信息时，存储取指示窗口的指令字节。第一压缩器被配置为将第一预解码信息和第一分支信息压缩成组合的预解码/分支信息。第一解压缩器被配置为对存储在第二存储器中的至少一些指令字节进行解码，以将组合的预解码/转移信息转换成对应于第一预解码信息的未压缩版本的第二预解码信息，以存储在第三存储器中。

2. 发明申请

US20080140993A1 FETCH ENGINE MONITORING DEVICE AND METHOD THEREOF 审中-公开
标题翻译： FETCH发动机监控装置及其方法
公开(公告)号：US20080140993A1
公开(公告)日：2008-06-12
申请号：US11608691
申请日：2006-12-08
申请人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
发明人： Ravindra N. Bhargava , Benjamin T. Sander , David Neal Suggs
IPC分类号： G06F9/312
CPC分类号： G06F11/3419 , G06F11/3471 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.
摘要翻译：根据本公开的具体实施例，硬件周期性地监视取出周期，其获取与地址相关联的数据，以确定与获取周期相关联的性能参数。与获取周期的持续时间相关的信息被保持，以及指示与获取周期相关的各种状态和数据值的发生的信息。例如，在获取循环期间处理的虚拟地址被保存在包含提取引擎的集成电路中。与流水线的执行引擎上的指令执行相关联的其他与性能相关的参数也被周期性地监视。然而，提取引擎的监视性能与监视与执行引擎的性能相关的事件分离。

3. 发明授权

US07840786B2 Techniques for storing instructions and related information in a memory hierarchy 有权
标题翻译：用于将指令和相关信息存储在存储器层次结构中的技术
公开(公告)号：US07840786B2
公开(公告)日：2010-11-23
申请号：US11735567
申请日：2007-04-16
申请人： David Neal Suggs
发明人： David Neal Suggs
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/30152 , G06F9/30156 , G06F9/3017 , G06F9/30178 , G06F9/3806 , G06F9/382 , G06F9/3844
摘要： A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory.
摘要翻译：存储器子系统包括第一存储器，第二存储器，第一压缩器和第一解压缩器。第一存储器被配置为存储取出窗口的指令字节，并且存储表征提取窗口的指令字节的第一预解码信息和第一分支信息。第二存储器被配置为在从第一存储器消除指令字节并存储也表征获取窗口的指令字节的组合预解码/转移信息时，存储取指示窗口的指令字节。第一压缩器被配置为将第一预解码信息和第一分支信息压缩成组合的预解码/分支信息。第一解压缩器被配置为对存储在第二存储器中的至少一些指令字节进行解码，以将组合的预解码/分支信息转换成对应于第一预解码信息的未压缩版本的第二预解码信息，以存储在第三存储器中。

4. 发明授权

US06253304B1 Collation of interrupt control devices 有权
标题翻译：中断控制装置的整理
公开(公告)号：US06253304B1
公开(公告)日：2001-06-26
申请号：US09224821
申请日：1999-01-04
申请人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
发明人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
IPC分类号： G06F946
CPC分类号： G06F9/4812
摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.
摘要翻译：第一和第二局部中断控制器设置在单个集成电路上。第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

5. 发明授权

US06263385B1 PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus 失效
标题翻译： PC并行端口结构分为两个通过串行总线互连的集成电路
公开(公告)号：US06263385B1
公开(公告)日：2001-07-17
申请号：US08955327
申请日：1997-10-20
申请人： Dale E. Gulick , David Neal Suggs
发明人： Dale E. Gulick , David Neal Suggs
IPC分类号： G06F1300
CPC分类号： G06F13/4004
摘要： A first and second integrated circuit contain respectively a first and second portion of a parallel port, the first portion includes control, configuration, data and status registers and the second portion includes parallel port input and output terminals. A bus couples the first and second integrated circuits and transfers parallel port control and data information between the first and second integrated circuits. The bus includes a clock line providing a clock signal. The bus also includes a data out line that serially transfers output control and data bits from the first to the second integrated circuit, the data and control bits to be provided to the parallel port output terminals on the second integrated circuit. The bus also includes a data in line providing input data and control information from the terminals of the parallel port to the first integrated circuit. The bus provides data either substantially continuously in frames defined by a frame sync or uses a start bit to go from an idle state to a data transfer state according to the read and write operations of the parallel port. The mode of operation of the parallel port determines whether data is transferred continuously in frames or after a start bit.
摘要翻译：第一和第二集成电路分别包含并行端口的第一和第二部分，第一部分包括控制，配置，数据和状态寄存器，第二部分包括并行端口输入和输出端子。总线耦合第一和第二集成电路，并且在第一和第二集成电路之间传送并行端口控制和数据信息。总线包括提供时钟信号的时钟线。总线还包括从第一至第二集成电路串行传输输出控制和数据位的数据输出线，将要提供给第二集成电路上的并行端口输出端的数据和控制位。该总线还包括一行数据，提供从并行端口到第一集成电路的端子的输入数据和控制信息。总线基本上连续地在由帧同步定义的帧中提供数据，或者根据并行端口的读取和写入操作，使起始位从空闲状态变为数据传输状态。并行端口的操作模式确定数据是以帧为单位还是在起始位之后连续传输。

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