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1. 发明授权

US06253304B1 Collation of interrupt control devices 有权
标题翻译：中断控制装置的整理
公开(公告)号：US06253304B1
公开(公告)日：2001-06-26
申请号：US09224821
申请日：1999-01-04
申请人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
发明人： Larry Hewitt , David Neal Suggs , Greg Smaus , Derrick R. Meyer
IPC分类号： G06F946
CPC分类号： G06F9/4812
摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.
摘要翻译：第一和第二局部中断控制器设置在单个集成电路上。第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

2. 发明授权

US06339808B1 Address space conversion to retain software compatibility in new architectures 有权
标题翻译：地址空间转换，以保持新体系结构中的软件兼容性
公开(公告)号：US06339808B1
公开(公告)日：2002-01-15
申请号：US09224820
申请日：1999-01-04
申请人： Larry Hewitt , Greg Smaus
发明人： Larry Hewitt , Greg Smaus
IPC分类号： G06F1324
CPC分类号： G06F13/24 , G06F13/404
摘要： A multi-processor computer system includes at least a first and second processor coupled to a host bus. The first processor accesses a first set of registers using a first plurality of addresses over the host bus. A second processor accesses a second set of registers using the first plurality of addresses over the host bus. A first integrated circuit forms a bridge between the host bus and an input/output bus. The first integrated circuit receives access requests for the first and second sets of registers from the first and second processors, respectively. A second integrated circuit, coupled to the input/output bus, includes a first and a second local interrupt controller, the first and second sets of registers being part of the first and second local interrupt controllers. The first integrated circuit, responsive to an access request from one of the processors to one of the first plurality of addresses, outputs information on the input/output bus indicating the address of the register being accessed and which of the first and second processors made the access request, thereby specifying one of the first and second sets of registers.
摘要翻译：多处理器计算机系统至少包括耦合到主机总线的第一和第二处理器。第一处理器使用主机总线上的第一多个地址访问第一组寄存器。第二处理器使用主机总线上的第一多个地址访问第二组寄存器。第一集成电路在主机总线和输入/输出总线之间形成一个桥。第一集成电路分别从第一和第二处理器接收针对第一和第二组寄存器的访问请求。耦合到输入/输出总线的第二集成电路包括第一和第二局部中断控制器，第一和第二组寄存器是第一和第二局部中断控制器的一部分。第一集成电路响应于从处理器之一到第一多个地址之一的访问请求，输出关于输入/输出总线的信息，指示正在被访问的寄存器的地址，以及第一和第二处理器中的哪一个使访问请求，从而指定第一和第二组寄存器之一。

3. 发明授权

US08244950B2 Buffering non-posted read commands and responses 有权
标题翻译：缓冲非发布的读取命令和响应
公开(公告)号：US08244950B2
公开(公告)日：2012-08-14
申请号：US10285931
申请日：2002-11-01
申请人： Frank Barth , Larry Hewitt , Joerg Winkler , Paul Miranda
发明人： Frank Barth , Larry Hewitt , Joerg Winkler , Paul Miranda
IPC分类号： G06F3/00 , G06F5/00 , G06F13/36
CPC分类号： G06F13/4059
摘要： An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.
摘要翻译：提供了一种在南桥或I / O集线器或类似设备中使用的改进的接口技术，其中从至少一个请求者接收非发布的读取请求，并且发送基于这些请求的上行命令。接收响应数据以回复先前发送的命令，并且响应基于响应数据被发送到至少一个请求者。提供缓冲单元，用于存储识别已发送或尚待发送的命令的命令识别数据，以及指定已被接收引擎接收到的响应数据的响应可用性数据。改进可能会使多个未完成的读取请求。

4. 发明申请

US20060238267A1 Zoned thermal monitoring 有权
标题翻译：分区热监测
公开(公告)号：US20060238267A1
公开(公告)日：2006-10-26
申请号：US11110379
申请日：2005-04-20
申请人： Michael Bienek , Larry Hewitt , Huining Liu
发明人： Michael Bienek , Larry Hewitt , Huining Liu
IPC分类号： H03L1/00
CPC分类号： H01L23/34 , G01K7/42 , G01K7/425 , G01K15/00 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.
摘要翻译：集成电路包括提供感测温度的指示的第一温度感测装置，与第一温度感测装置相邻定位的相关振荡器电路，多个其它振荡器电路以及存储与至少第一温度相关的校准因子的存储位置感测装置和多个其它振荡器电路。温度计算电路确定集成电路中各种位置的温度。每个温度根据其他振荡器中的相应振荡器的振荡频率，相关环形振荡器的振荡频率，第一温度感测装置的温度和一个或多个存储的校准因子来确定。

5. 发明授权

US06389526B1 Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system 有权
标题翻译：用于选择性地停止由耦合到多处理器系统的设备发起的中断请求的电路和方法
公开(公告)号：US06389526B1
公开(公告)日：2002-05-14
申请号：US09382360
申请日：1999-08-24
申请人： James B. Keller , Dale Gulick , Larry Hewitt , Geoffrey Strongin
发明人： James B. Keller , Dale Gulick , Larry Hewitt , Geoffrey Strongin
IPC分类号： G06F1316
CPC分类号： G06F15/167 , G06F13/24
摘要： A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.
摘要翻译：提供了一种电路和方法，用于选择性地停止与多处理器系统耦合的发起设备的中断请求。多处理器系统包括多个电路节点，每个电路节点都耦合到单独的存储器。耦合到第一电路节点的I / O桥被配置为生成非相干存储器访问命令分组和非相干中断命令分组。第一电路节点还响应于接收到非相干中断命令分组而产生相干中断命令分组。第一电路节点将相干中断命令分组发送到另一个电路节点，可能是第二电路节点。然而，相干中断命令分组的传输可能被延迟。传输的任何延迟都是基于非相干命令包的管道标识的比较。

6. 发明授权

US5761434A Digital audio system including a software controlled phase lock loop for synchronizing audio sources to a common clock source 失效
标题翻译：数字音频系统包括用于将音频源同步到公共时钟源的软件控制的锁相环
公开(公告)号：US5761434A
公开(公告)日：1998-06-02
申请号：US812217
申请日：1997-03-06
申请人： Larry Hewitt
发明人： Larry Hewitt
IPC分类号： G06F3/16 , H03L7/085 , H04J3/06 , H04S1/00 , H04N1/36
CPC分类号： H04S1/007 , G06F3/16 , H04J3/0632 , H03L7/085
摘要： A system and method for software control of a phase lock loop which accomplishes synchronization between sampled input audio voice signals and a clock controlling the output signal sampling rate. A memory queue is used to buffer input voice data sampled at an input sampling rate. A DSP retrieves stored voice data from the memory queue at a read rate which is periodically adjusted by the DSP according to the number of stored voice data samples remaining in the queue. The read rate is adjusted so as to maintain the number of stored voice data samples at substantially half of the queue capacity.
摘要翻译：用于软件控制锁相环的系统和方法，其实现采样输入音频语音信号与控制输出信号采样率的时钟之间的同步。存储器队列用于缓冲以输入采样率采样的输入语音数据。 DSP以读取速率从存储器队列检索存储的语音数据，该读取速率根据存储在队列中的语音数据样本数量，由DSP周期性地调整。调整读取速率，以将存储的语音数据样本的数量保持在队列容量的大致一半。

7. 发明申请

US20070234080A1 Power management in a communication link 有权
标题翻译：通信链路中的电源管理
公开(公告)号：US20070234080A1
公开(公告)日：2007-10-04
申请号：US11482269
申请日：2006-07-07
申请人： Paul Mackey , Paul Miranda , Larry Hewitt , Jonathan Owen
发明人： Paul Mackey , Paul Miranda , Larry Hewitt , Jonathan Owen
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters enter a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.
摘要翻译：计算机系统包括通过通信链路耦合的第一和第二集成电路。通信链路以省电模式运行，其中数据不通过链路发送。周期性地，通信链路进入训练阶段，在该训练阶段通过通信链路在预定时间段内传送训练模式。在预定时间段过去之后，通信链路返回到省电模式。与通信链路分离并且耦合在第一和第二集成电路之间的至少一个边带信号用于指示何时从功率节省模式进入训练阶段并退出训练阶段并返回到省电模式。

8. 发明申请

US20070081575A1 Method and apparatus for temperature sensing in integrated circuits 失效
标题翻译：集成电路中温度检测的方法和装置
公开(公告)号：US20070081575A1
公开(公告)日：2007-04-12
申请号：US11246855
申请日：2005-10-07
申请人： Huining Liu , Larry Hewitt
发明人： Huining Liu , Larry Hewitt
IPC分类号： G01K3/00
CPC分类号： G01K7/203
摘要： A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a reference unit coupled to provide a reference temperature to the control logic unit and a reference sensor coupled to provide a signal having a reference frequency to the control logic unit. The reference unit and the reference sensor are located near each other. The control logic unit is configured to correlate the reference frequency received from the reference sensor with the reference temperature received from the reference unit. The control logic unit is further configured to determine the temperature of each of the remote temperature sensors based on this correlation, and also configured to determine the maximum temperature of all of the temperature sensors.
摘要翻译：一种用于IC中温度感测的方法和装置。 IC包括多个远程温度传感器，每个远程温度传感器都耦合到控制逻辑单元。多个远程温度传感器可以分布在整个集成电路中。该集成电路包括一个参考单元，该参考单元被耦合以向控制逻辑单元提供参考温度，以及一个参考传感器，该参考传感器被耦合以向控制逻辑单元提供具有参考频率的信号。参考单元和参考传感器彼此靠近。控制逻辑单元被配置为将从参考传感器接收的参考频率与从参考单元接收的参考温度相关联。控制逻辑单元还被配置为基于该相关性来确定每个远程温度传感器的温度，并且还被配置为确定所有温度传感器的最高温度。

9. 发明授权

US06173348B2 Using a control line to insert a control message during a data transfer on a bus 有权
标题翻译：在总线上的数据传输期间使用控制线插入控制消息
公开(公告)号：US06173348B2
公开(公告)日：2001-01-09
申请号：US09494873
申请日：2000-01-31
申请人： Larry Hewitt
发明人： Larry Hewitt
IPC分类号： G06F1300
CPC分类号： G06F13/4256
摘要： Asynchronous and isochronous data is transferred over a bus connecting a first device and a second device. Data is selectably transferred over the bus in either asynchronous priority mode or isochronous priority mode. Asynchronous priority mode gives priority to transfer of the asynchronous data and isochronous priority mode gives priority to transfer of the isochronous data. In addition, data transferred over the bus is selectably transferred in either whole-bus mode: in which the entire data bus transfers data in one direction or in or half-bus mode in which portions of the data bus may transfer data in different directions.
摘要翻译：异步和同步数据通过连接第一设备和第二设备的总线传送。在异步优先模式或等时优先模式下，通过总线可选择地传送数据。异步优先模式优先转移异步数据，等时优先模式优先转发等时数据。另外，通过总线传输的数据可选择性地以全母线模式传输：其中整个数据总线在一个方向或半总线模式下传输数据，其中数据总线的一部分可以在不同方向上传送数据。

10. 发明授权

US5901333A Vertical wavetable cache architecture in which the number of queues is substantially smaller than the total number of voices stored in the system memory 失效
标题翻译：其中队列数量显着小于存储在系统存储器中的语音总数的垂直波度缓存架构
公开(公告)号：US5901333A
公开(公告)日：1999-05-04
申请号：US687859
申请日：1996-07-26
申请人： Larry Hewitt
发明人： Larry Hewitt
IPC分类号： G10H7/00 , G06F13/00
CPC分类号： G10H7/002 , G10H2230/031 , G10H2240/275
摘要： A wavetable cache for an audio synthesizer which synthesizes music signals from voice data in a pooled memory uses a vertical architecture cache to communicate data from the memory to an audio signal processor. The vertical architecture cache includes a substantially limited number of queues, corresponding to only a fraction of the voices stored in the main memory and processed in the audio signal processor. A plurality of samples are transferred in a batch mode from the memory via a system bus to a queue. The samples are subsequently processed and accumulated for the entire plurality of samples by the audio signal processor. The limited number of queues are shared among the different voices in a round-robin fashion.
摘要翻译：用于从汇集的存储器中的语音数据合成音乐信号的音频合成器的波形缓存器使用垂直架构高速缓存来将数据从存储器传送到音频信号处理器。垂直架构高速缓存包括基本上有限数量的队列，对应于仅存储在主存储器中并在音频信号处理器中处理的语音的一小部分。多个样本以批处理模式从存储器经由系统总线传送到队列。随后通过音频信号处理器对样本进行整个多个样本的处理和累积。有限数量的队列以循环方式在不同的声音之间共享。

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