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1. 发明授权

US07809903B2 Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions 有权
标题翻译：协调访问硬件事务内存事务和软件事务内存事务的内存位置
公开(公告)号：US07809903B2
公开(公告)日：2010-10-05
申请号：US11303529
申请日：2005-12-15
申请人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard L. Hudson , Haitham Akkary , Ravi Rajwar
发明人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard L. Hudson , Haitham Akkary , Ravi Rajwar
IPC分类号： G06F12/12
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了一种用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务发起访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，故障返回到硬件事务请求。

2. 发明申请

US20070239942A1 Transactional memory virtualization 有权
标题翻译：事务性内存虚拟化
公开(公告)号：US20070239942A1
公开(公告)日：2007-10-11
申请号：US11394622
申请日：2006-03-30
申请人： Ravi Rajwar , Haitham Akkary , Konrad Lai
发明人： Ravi Rajwar , Haitham Akkary , Konrad Lai
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
摘要翻译：描述了以虚拟化模式提供事务性存储器执行的方法和装置。在一个实施例中，对应于事务存储器访问请求的数据可以在与事务存储器访问请求相对应的操作引起溢出并且可以针对溢出的发生更新存储的值之后存储在存储器的一部分中。

3. 发明申请

US20070143287A1 Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions 有权
标题翻译：协调访问硬件事务内存事务和软件事务内存事务的内存位置
公开(公告)号：US20070143287A1
公开(公告)日：2007-06-21
申请号：US11303529
申请日：2005-12-15
申请人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard Hudson , Haitham Akkary , Ravi Rajwar
发明人： Ali-Reza Adl-tabatabai , Bratin Saha , Richard Hudson , Haitham Akkary , Ravi Rajwar
IPC分类号： G06F17/30
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了一种用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务发起访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，故障返回到硬件事务请求。

4. 发明申请

US20050120191A1 Checkpoint-based register reclamation 审中-公开
标题翻译：基于检查点的寄存器回收
公开(公告)号：US20050120191A1
公开(公告)日：2005-06-02
申请号：US10724874
申请日：2003-12-02
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： A processor enabled with checkpoints may be used to recover registers using counter entry and release.
摘要翻译：启用检查点的处理器可用于使用计数器条目和释放来恢复寄存器。

5. 发明授权

US06247121B1 Multithreading processor with thread predictor 有权
标题翻译：具有线程预测器的多线程处理器
公开(公告)号：US06247121B1
公开(公告)日：2001-06-12
申请号：US09157791
申请日：1998-09-21
申请人： Haitham Akkary , Quinn A. Jacobson
发明人： Haitham Akkary , Quinn A. Jacobson
IPC分类号： C06F1500
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/3834 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3863
摘要： In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction. The final retirement logic may control whether the actual thread is retired, and wherein if the actual thread is retired, the state machine associated with the actual thread is updated in a take direction. The circuitry may be used in connection with a multi-threading processor that detects speculation errors involving thread dependencies in execution of the actual threads and re-executes instructions associated with the speculation errors from trace buffers outside an execution pipeline.
摘要翻译：在一个实施例中，处理器包括线程管理逻辑，其包括具有状态机的线程预测器，以指示是否采取线程创建机会。该处理器包括一个预测器训练机制，用于接收退休指令，并从退休指令中识别潜在的线程，并确定一个可能的线程是否满足线程精度的测试，并且如果该测试得到满足，那么状态机与感兴趣的潜在线程相关联的更新在取向方向上，并且如果不满足测试，则状态机以不采取方向更新。线程管理逻辑可以控制实际线程的创建，并且还可以包括复位逻辑以控制实际线程是否被重置，并且其中如果实际线程被重置，则与实际线程相关联的状态机之一被更新为不采用方向。最终退休逻辑可以控制实际线程是否退休，并且其中如果实际线程已经退休，则与实际线程相关联的状态机在取向方向上被更新。电路可以与多线程处理器结合使用，该多线程处理器检测涉及执行实际线程中的线程相关性的推测误差，并重新执行与执行流水线之外的跟踪缓冲器的推测错误相关联的指令。

6. 发明授权

US5860154A Method and apparatus for calculating effective memory addresses 失效
标题翻译：用于计算有效存储器地址的方法和装置
公开(公告)号：US5860154A
公开(公告)日：1999-01-12
申请号：US778969
申请日：1997-01-06
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mark A. Timko
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mark A. Timko
IPC分类号： G06F9/318 , G06F9/355 , G06F12/00
CPC分类号： G06F9/3555 , G06F9/3017
摘要： A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.
摘要翻译：为微处理器提供宏指令，允许程序员指定基值，索引，比例因子和位移值，用于计算有效地址并在单个时钟周期内返回该结果。宏指令被转换为微操作，其被提供给具有用于执行计算的所需源操作数的单周期执行单元。在单周期执行单元内，将索引和比例因子提供给用于乘以两个值的左移位器。左移操作的结果被加到底座和位移之和上。这导致有效地址然后从单周期执行单元返回到预定的目的地。这提供了独立于存储器系统执行单元的单周期流水线执行单元中的有效地址的计算。

7. 发明授权

US5717882A Method and apparatus for dispatching and executing a load operation to memory 失效
标题翻译：用于调度和执行对存储器的加载操作的方法和装置
公开(公告)号：US5717882A
公开(公告)日：1998-02-10
申请号：US764643
申请日：1996-12-11
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Michael A. Fetterman
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/312 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836
摘要： A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.
摘要翻译：一种用于使用计算机系统中的处理器执行操作的方法和装置。通过使用调度管道和存储器执行管线来执行加载操作。调度管道调度处理器执行的加载操作，而存储器执行流水线控制对存储器的加载操作的执行。本发明通过在执行加载操作期间耦合两条管线的执行来减少执行加载操作所涉及的延迟。

8. 发明授权

US5708843A Method and apparatus for handling code segment violations in a computer system 失效
标题翻译：在计算机系统中处理代码段违规的方法和装置
公开(公告)号：US5708843A
公开(公告)日：1998-01-13
申请号：US544558
申请日：1995-10-18
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3865
摘要： A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.
摘要翻译：在处理器中发出存储器操作。在检测到存储器操作产生代码段违反并且在退出时存储器操作被阻止的情况下，产生阻塞信号以阻止响应于存储器操作的总线访问。第二个信号表示内存操作完成。

9. 发明授权

US5664137A Method and apparatus for executing and dispatching store operations in a computer system 失效
标题翻译：用于在计算机系统中执行和调度存储操作的方法和装置
公开(公告)号：US5664137A
公开(公告)日：1997-09-02
申请号：US525499
申请日：1995-09-07
申请人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
发明人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
IPC分类号： G06F9/312 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3889 , G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.
摘要翻译：一种用于执行存储操作的方法和装置，包括计算地址并获得用于存储操作的数据。地址表示要存储数据的存储器位置。一旦计算了地址并获得了数据，存储操作就被提交到处理器状态。可以将存储操作调度到存储器以完成存储操作的执行。

10. 发明授权

US5588126A Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system 失效
标题翻译：在无序执行计算机系统上缓存存储数据的方法和装置
公开(公告)号：US5588126A
公开(公告)日：1996-12-24
申请号：US446030
申请日：1995-05-19
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3834
摘要： In an out-of-order execution computer system, a store buffer is conditionally signaled to output buffered store data of buffered memory store operations, when a buffered memory load operation is being executed. The determination on whether to signal the store buffer or not is made using control information that includes the allocation state of the store buffer at the time the memory load operation being executed was issued. The allocation state includes the identification of the buffer slot storing the last memory store operation stored into the store buffer, and the wraparound state of a circular wraparound allocation approach employed to allocate buffer slots to the memory store operations, at the time the memory load operation being executed was issued.
摘要翻译：在无序执行计算机系统中，当执行缓冲存储器加载操作时，存储缓冲器有条件地发信号通知缓冲存储器存储操作的缓冲存储数据。使用包含在执行存储器加载操作的时刻存储缓冲器的分配状态的控制信息来确定是否发出存储缓冲器的信号。分配状态包括存储存储到存储缓冲器中的最后存储器存储操作的缓冲器槽的标识，以及在存储器加载操作时用于将缓冲器时隙分配给存储器存储操作的循环环绕分配方法的环绕状态正在执行中。

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