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1. 发明授权

US08987098B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08987098B2
公开(公告)日：2015-03-24
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

2. 发明授权

US08889509B2 Charge trapping devices with field distribution layer over tunneling barrier 有权
标题翻译：带隧道势垒的场分布层的电荷俘获装置
公开(公告)号：US08889509B2
公开(公告)日：2014-11-18
申请号：US13210202
申请日：2011-08-15
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： H01L21/336 , H01L29/792 , H01L21/28 , H01L29/788 , H01L29/423 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/788 , H01L29/792
摘要： A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.
摘要翻译：一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

3. 发明申请

US20140198576A1 PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES 审中-公开
标题翻译：用于减少堆叠存储器结构中的程序干扰的编程技术
公开(公告)号：US20140198576A1
公开(公告)日：2014-07-17
申请号：US13827475
申请日：2013-03-14
申请人： Shuo-Nan Hung , HANG-TING LUE , TI-WEN CHEN , SHIH-LIN HUANG , KUO-PIN CHANG , CHIH-CHANG HSIEH , CHUN-HSIUNG HUNG
发明人： Shuo-Nan Hung , HANG-TING LUE , TI-WEN CHEN , SHIH-LIN HUANG , KUO-PIN CHANG , CHIH-CHANG HSIEH , CHUN-HSIUNG HUNG
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2216/14 , H01L27/11551 , H01L27/11578
摘要： A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.
摘要翻译：描述用于对具有多层存储器单元的堆叠存储器结构进行编程的编程偏置技术。该技术包括响应于程序指令的控制器电路，以在特定多位地址的单元堆栈中的目标单元格中编程数据。电路被配置为使用单元格堆栈中的单元格分配给多个单元组，并且迭代地执行依次选择多个集合中的每一个的设置程序操作。每个迭代包括对多个组中的其他单元中的所有单元施加抑制电压。此外，每组层包括一个或两个子集，并且存在至少两个层，其中一组将每个子集分隔开。

4. 发明授权

US08759899B1 Integration of 3D stacked IC device with peripheral circuits 有权
标题翻译：集成3D堆叠式IC器件与外围电路
公开(公告)号：US08759899B1
公开(公告)日：2014-06-24
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L29/788
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

5. 发明申请

US20130175598A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130175598A1
公开(公告)日：2013-07-11
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

6. 发明授权

US08482052B2 Silicon on insulator and thin film transistor bandgap engineered split gate memory 有权
标题翻译：硅绝缘体和薄膜晶体管带隙设计的分离栅极存储器
公开(公告)号：US08482052B2
公开(公告)日：2013-07-09
申请号：US12056489
申请日：2008-03-27
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0483 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792
摘要： Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.
摘要翻译：薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

7. 发明授权

US08363476B2 Memory device, manufacturing method and operating method of the same 有权
标题翻译：存储器件，制造方法和操作方法相同
公开(公告)号：US08363476B2
公开(公告)日：2013-01-29
申请号：US13009464
申请日：2011-01-19
申请人： Hang-Ting Lue , Shih-Hung Chen
发明人： Hang-Ting Lue , Shih-Hung Chen
IPC分类号： G11C16/00
CPC分类号： H01L29/7926 , G11C16/0466 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.
摘要翻译：提供了一种存储器件，其制造方法和操作方法。存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。堆叠结构设置在基板上。每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。串选择线，字线和接地选择线通过绝缘线彼此分离。通道元件设置在堆叠结构之间。电介质元件设置在通道元件和堆叠结构之间。源元件设置在基板的上表面和通道元件的下表面之间。位线设置在通道元件的上表面上。

8. 发明授权

US08343840B2 Blocking dielectric engineered charge trapping memory cell with high speed erase 有权
标题翻译：阻塞具有高速擦除的介电工程电荷捕获存储单元
公开(公告)号：US08343840B2
公开(公告)日：2013-01-01
申请号：US12763006
申请日：2010-04-19
申请人： Sheng-Chih Lai , Hang-Ting Lue , Chien-Wei Liao
发明人： Sheng-Chih Lai , Hang-Ting Lue , Chien-Wei Liao
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0466 , G11C16/0483 , H01L21/28282 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.
摘要翻译：带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括通道由工程隧道电介质。

9. 发明授权

US08324681B2 Stacked non-volatile memory device and methods for fabricating the same 有权
标题翻译：堆叠的非易失性存储器件及其制造方法
公开(公告)号：US08324681B2
公开(公告)日：2012-12-04
申请号：US13162386
申请日：2011-06-16
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/792
摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
摘要翻译：堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。该器件可以配置为NAND操作。

10. 发明申请

US20120281478A1 THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING 有权
标题翻译：具有二极管缠绕的热辅助闪存
公开(公告)号：US20120281478A1
公开(公告)日：2012-11-08
申请号：US13458970
申请日：2012-04-27
申请人： HANG-TING LUE , Chun-Hsiung Hung
发明人： HANG-TING LUE , Chun-Hsiung Hung
IPC分类号： G11C16/04 , H01L21/8239
CPC分类号： G11C16/08 , G11C5/025 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/3495 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/1021 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42324 , H01L29/42328 , H01L29/4234 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.
摘要翻译：存储器包括包括行和列的存储单元阵列。存储器包括耦合到字线的电路，在施加与第一偏置电压不同的第二偏置电压的同时，将第一偏置电压施加到阵列中的字线或字线上的第一组间隔开的位置，在字线或字线上的一组间隔开的位置，第一组间隔开的位置中的位置在第二组间隔开的位置中的位置之间交错，从而在第一和第二位置之间的位置之间感应出电流导致字线或字线加热的位置集合。

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