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1. 发明授权

US09048341B2 Integrated circuit capacitor and method 有权
标题翻译：集成电路电容及方法
公开(公告)号：US09048341B2
公开(公告)日：2015-06-02
申请号：US13451428
申请日：2012-04-19
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh
IPC分类号： H01L21/02 , H01L49/02
CPC分类号： H01L28/91
摘要： An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.
摘要翻译：电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

2. 发明授权

US09035275B2 Three dimensional memory array adjacent to trench sidewalls 有权
标题翻译：与沟槽侧壁相邻的三维存储器阵列
公开(公告)号：US09035275B2
公开(公告)日：2015-05-19
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

3. 发明授权

US08987098B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08987098B2
公开(公告)日：2015-03-24
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

4. 发明授权

US08944739B2 Loadport bridge for semiconductor fabrication tools 有权
标题翻译：用于半导体制造工具的承载桥
公开(公告)号：US08944739B2
公开(公告)日：2015-02-03
申请号：US13486024
申请日：2012-06-01
申请人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
发明人： Shih-Hung Chen , Ying Xiao , Chin-Hsiang Lin
IPC分类号： H01L21/677
CPC分类号： H01L21/6773 , H01L21/67733 , H01L21/67775
摘要： A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.
摘要翻译：一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。在一个实施例中，该装置是装载端口机构，其包括具有第一和第二安装端的外壳，每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合，以及至少一个可运输的晶片传送机械手在对接端口之间的晶片。晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输，而不依赖于FAB的自动化材料处理系统（AMHS），用于在诸如FOUP或其它晶片载体之间的体晶片传输。

5. 发明授权

US08836137B2 Method for creating a 3D stacked multichip module 有权
标题翻译：创建3D堆叠多芯片模块的方法
公开(公告)号：US08836137B2
公开(公告)日：2014-09-16
申请号：US13451411
申请日：2012-04-19
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L21/00
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/16146 , H01L2224/24011 , H01L2224/24146 , H01L2224/2919 , H01L2224/32145 , H01L2224/33181 , H01L2224/82031 , H01L2224/821 , H01L2224/83005 , H01L2224/83191 , H01L2224/8385 , H01L2224/9202 , H01L2225/06544 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014 , H01L2224/82
摘要： A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
摘要翻译： 3D堆叠多芯片模块包括一堆W IC芯片。每个管芯具有图案化导体层，其包括与电导体的电接触区域，并且在一些示例中包括衬底上的器件电路。堆叠管芯的电导体对齐。电连接器延伸到堆叠中以接触电导体上的着陆焊盘，以产生3D堆叠多芯片模块。电连接器可以穿过电接触区域中的垂直通孔。着陆垫可以布置成阶梯式的台阶。堆叠的多芯片模块可以使用一组N个蚀刻掩模制成，其中2N-1小于W且2N大于或等于W，其中蚀刻掩模交替地覆盖并暴露每个掩模的2n-1个着陆焊盘n = 1，2。。。 N.

6. 发明申请

US20140193973A1 METHOD FOR FORMING INTERLAYER CONNECTORS TO A STACK OF CONDUCTIVE LAYERS 有权
标题翻译：将层间连接器形成到导电层堆叠的方法
公开(公告)号：US20140193973A1
公开(公告)日：2014-07-10
申请号：US13735922
申请日：2013-01-07
申请人： Shih-Hung CHEN
发明人： Shih-Hung CHEN
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/32139 , H01L21/76838 , H01L27/11548 , H01L27/11575
摘要： A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.
摘要翻译：一种方法形成延伸到与电介质层交错的W导电层的堆叠的导体层的层间连接。使用一组M蚀刻掩模蚀刻堆叠以暴露W-1导电层的着陆区域。对于从0到M-1的每个蚀刻掩模m，m，在每个修整步骤之后，存在第一蚀刻步骤，至少一个掩模修剪步骤和随后的蚀刻步骤。蚀刻掩模可以覆盖着陆区域的Nm + 1，并且开放蚀刻区域可以覆盖着陆区域的Nm。 N等于2加上修剪步骤的数量。可以进行修整步骤，使得增大的开口蚀刻区域覆盖附加的1 / N的着陆区域。在去除步骤期间可以屏蔽堆叠表面的一部分以产生没有接触开口的虚拟区域。

7. 发明授权

US08759899B1 Integration of 3D stacked IC device with peripheral circuits 有权
标题翻译：集成3D堆叠式IC器件与外围电路
公开(公告)号：US08759899B1
公开(公告)日：2014-06-24
申请号：US13739914
申请日：2013-01-11
申请人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
发明人： Hang-Ting Lue , Yi-Hsuan Hsiao , Shih-Hung Chen , Yen-Hao Shih
IPC分类号： H01L29/788
CPC分类号： H01L22/12 , H01L22/20 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L29/0649
摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
摘要翻译：集成电路器件包括包括第一区域和第二区域的衬底。在第一区域形成凹坑。与绝缘层交替的一叠有源层沉积在凹坑中。堆叠包括特定的绝缘层。特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

8. 发明授权

US08759217B1 Method for forming interlayer connectors to a stack of conductive layers 有权
标题翻译：用于将层间连接器形成到导电层的叠层的方法
公开(公告)号：US08759217B1
公开(公告)日：2014-06-24
申请号：US13735922
申请日：2013-01-07
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/32139 , H01L21/76838 , H01L27/11548 , H01L27/11575
摘要： A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.
摘要翻译：一种方法形成延伸到与电介质层交错的W导电层的堆叠的导体层的层间连接。使用一组M蚀刻掩模蚀刻堆叠以暴露W-1导电层的着陆区域。对于从0到M-1的每个蚀刻掩模m，m，在每个修整步骤之后，存在第一蚀刻步骤，至少一个掩模修剪步骤和随后的蚀刻步骤。蚀刻掩模可以覆盖着陆区域的Nm + 1，并且开放蚀刻区域可以覆盖着陆区域的Nm。 N等于2加上修剪步骤的数量。可以进行修整步骤，使得增大的开口蚀刻区域覆盖附加的1 / N的着陆区域。在去除步骤期间可以屏蔽堆叠表面的一部分以产生没有接触开口的虚拟区域。

9. 发明申请

US20130175598A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130175598A1
公开(公告)日：2013-07-11
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

10. 发明授权

US08363476B2 Memory device, manufacturing method and operating method of the same 有权
标题翻译：存储器件，制造方法和操作方法相同
公开(公告)号：US08363476B2
公开(公告)日：2013-01-29
申请号：US13009464
申请日：2011-01-19
申请人： Hang-Ting Lue , Shih-Hung Chen
发明人： Hang-Ting Lue , Shih-Hung Chen
IPC分类号： G11C16/00
CPC分类号： H01L29/7926 , G11C16/0466 , G11C16/3418 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.
摘要翻译：提供了一种存储器件，其制造方法和操作方法。存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。堆叠结构设置在基板上。每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。串选择线，字线和接地选择线通过绝缘线彼此分离。通道元件设置在堆叠结构之间。电介质元件设置在通道元件和堆叠结构之间。源元件设置在基板的上表面和通道元件的下表面之间。位线设置在通道元件的上表面上。

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